基于0.18 mm工艺设计了一种可集成到低电源电压数字IC或数模混合IC的上电复位电路。该POR(Power On Reset)具有电源上电和掉电检测功能,且对电源上电的速度不敏感,故可通过使用迟滞比较器实现对电源噪声的免疫。corner仿真结果表明,该...基于0.18 mm工艺设计了一种可集成到低电源电压数字IC或数模混合IC的上电复位电路。该POR(Power On Reset)具有电源上电和掉电检测功能,且对电源上电的速度不敏感,故可通过使用迟滞比较器实现对电源噪声的免疫。corner仿真结果表明,该电路可以实现大于100 ms的延时。相比于传统POR,该电路工作电压低、性能可靠、结构简单。展开更多
This paper presents a fully integrated 4 8GHz VCO with an invention——symmetrical noise filter technique.This VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0 25μm SMIC...This paper presents a fully integrated 4 8GHz VCO with an invention——symmetrical noise filter technique.This VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0 25μm SMIC CMOS process.The oscillator consumes 6mA from 2 5V supply.Another conventional VCO is also designed and simulated without symmetrical noise filter on the same process,which also consumes 6mA current and is with the same tuning.Simulation result describes that the first VCO’ phase noise is 6dBc/Hz better than the latter’s at the same offset frequency from 4 8GHz.Measured phase noise at 1MHz away from the carrier in this 4 8GHz VCO with symmetrical noise filter is -123 66dBc/Hz.This design is suitable for the usage in a phase locked loop and other consumer electronics.It is amenable for future technologies and allows easy porting to different CMOS manufacturing process.展开更多
A novel level-shift LDMOS （lateral double-diffused metal oxide semiconductor） structure with the HV （high voltage） -interconnection for a 600 V-HVIC （high voltage integrated circuit） on thick SOI （silicon on in...A novel level-shift LDMOS （lateral double-diffused metal oxide semiconductor） structure with the HV （high voltage） -interconnection for a 600 V-HVIC （high voltage integrated circuit） on thick SOI （silicon on insulator） is proposed. There are two original points in the proposed structure. One is the formation of the double floating p-layers under the HV-interconnection to prevent potential distribution in the drift from disturbing due to the HV-interconnection, and the other is a good combination between the LDMOS structure and multiple trench isolation to obtain the isolation performance over 600 V. From the proposed structure, the high blocking capability of the LDMOS, including both off- and on-breakdown voltages over 600 V and high hot carrier instability, and the isolation performance over 1,200 V can be obtained successfully. This paper will show numerical and experimental results in detail.展开更多
文摘基于0.18 mm工艺设计了一种可集成到低电源电压数字IC或数模混合IC的上电复位电路。该POR(Power On Reset)具有电源上电和掉电检测功能,且对电源上电的速度不敏感,故可通过使用迟滞比较器实现对电源噪声的免疫。corner仿真结果表明,该电路可以实现大于100 ms的延时。相比于传统POR,该电路工作电压低、性能可靠、结构简单。
文摘This paper presents a fully integrated 4 8GHz VCO with an invention——symmetrical noise filter technique.This VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0 25μm SMIC CMOS process.The oscillator consumes 6mA from 2 5V supply.Another conventional VCO is also designed and simulated without symmetrical noise filter on the same process,which also consumes 6mA current and is with the same tuning.Simulation result describes that the first VCO’ phase noise is 6dBc/Hz better than the latter’s at the same offset frequency from 4 8GHz.Measured phase noise at 1MHz away from the carrier in this 4 8GHz VCO with symmetrical noise filter is -123 66dBc/Hz.This design is suitable for the usage in a phase locked loop and other consumer electronics.It is amenable for future technologies and allows easy porting to different CMOS manufacturing process.
文摘A novel level-shift LDMOS （lateral double-diffused metal oxide semiconductor） structure with the HV （high voltage） -interconnection for a 600 V-HVIC （high voltage integrated circuit） on thick SOI （silicon on insulator） is proposed. There are two original points in the proposed structure. One is the formation of the double floating p-layers under the HV-interconnection to prevent potential distribution in the drift from disturbing due to the HV-interconnection, and the other is a good combination between the LDMOS structure and multiple trench isolation to obtain the isolation performance over 600 V. From the proposed structure, the high blocking capability of the LDMOS, including both off- and on-breakdown voltages over 600 V and high hot carrier instability, and the isolation performance over 1,200 V can be obtained successfully. This paper will show numerical and experimental results in detail.
