Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the s...Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.展开更多
The loss mechanisms of different passive devices （on-chip inductors and capacitors） on different substrates are analyzed and compared. OPS （oxidized porous silicon） and HR （high-resistivity） substrates are used ...The loss mechanisms of different passive devices （on-chip inductors and capacitors） on different substrates are analyzed and compared. OPS （oxidized porous silicon） and HR （high-resistivity） substrates are used as low-loss substrates for on-chip planar LPF （low pass filter） fabrication. For the study of substrate loss, a planar coil inductor is also designed. Simulation results show that Q （the quality factor） of the inductor on both substrates is over 20. Measurements of the LPF on OPS substrate give a - 3dB bandwidth of 2.9GHz and a midband insertion loss of 0.87dB at 500MHz. The LPF on HR substrate gives a - 3dB bandwidth of 2.3GHz and a midband insertion loss of 0.42dB at 500MHz.展开更多
Shanghai Changjiang Tunnel, 15 m in diameter, is one of the world＇s largest shield-driven tunnels in diameter. Tongji University has recently carried out a test on the full-scale three-ring lining structure of Changj...Shanghai Changjiang Tunnel, 15 m in diameter, is one of the world＇s largest shield-driven tunnels in diameter. Tongji University has recently carried out a test on the full-scale three-ring lining structure of Changjiang Tunnel. This paper introduces the testing processes, including loading apparatuses, test contents, test cases, etc., and makes comparison with other shield lining structure tests conducted before, and finally gives some evaluations on the design of the tunnel.展开更多
文摘Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.
文摘The loss mechanisms of different passive devices （on-chip inductors and capacitors） on different substrates are analyzed and compared. OPS （oxidized porous silicon） and HR （high-resistivity） substrates are used as low-loss substrates for on-chip planar LPF （low pass filter） fabrication. For the study of substrate loss, a planar coil inductor is also designed. Simulation results show that Q （the quality factor） of the inductor on both substrates is over 20. Measurements of the LPF on OPS substrate give a - 3dB bandwidth of 2.9GHz and a midband insertion loss of 0.87dB at 500MHz. The LPF on HR substrate gives a - 3dB bandwidth of 2.3GHz and a midband insertion loss of 0.42dB at 500MHz.
文摘Shanghai Changjiang Tunnel, 15 m in diameter, is one of the world＇s largest shield-driven tunnels in diameter. Tongji University has recently carried out a test on the full-scale three-ring lining structure of Changjiang Tunnel. This paper introduces the testing processes, including loading apparatuses, test contents, test cases, etc., and makes comparison with other shield lining structure tests conducted before, and finally gives some evaluations on the design of the tunnel.
