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一类性能好、复杂度低的纠错编码——乘加码
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作者 朱玉玲 谭莹 《现代电子技术》 2006年第3期1-3,9,共4页
对一类性能好且复杂度低的纠错编码技术——乘加码进行了介绍。他是在单校验位的Turbo乘积码(Single Parity Check Turbo Product Code)的基础上改进而来的,即由单校验位的Turbo乘积码作为外码,码率为1的递归卷积码作为内码串行级联而... 对一类性能好且复杂度低的纠错编码技术——乘加码进行了介绍。他是在单校验位的Turbo乘积码(Single Parity Check Turbo Product Code)的基础上改进而来的,即由单校验位的Turbo乘积码作为外码,码率为1的递归卷积码作为内码串行级联而成。介绍了乘加码的编码方式和译码方法,并给出了其性能分析。对于一定的分组长度,这类码表现出与Turbo码相近的性能,但其译码复杂度要远远低于Turbo码。 展开更多
关键词 乘加码 TPC/SPC(Single—Parity CHECK TURBO Product Code) 和积算法 纠错编码
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Optimization design of 24bit parallel MAC unit with saturation
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作者 张萌 贾俊波 《Journal of Southeast University(English Edition)》 EI CAS 2006年第4期475-478,共4页
An efficient design method for a 24 × 24 bit +48 bit parallel saturating multiply-accumulate (MAC) unit is described. The augend in the MAC is merged as a partial product into Wallace tree array. The optimized... An efficient design method for a 24 × 24 bit +48 bit parallel saturating multiply-accumulate (MAC) unit is described. The augend in the MAC is merged as a partial product into Wallace tree array. The optimized saturation detection logic is proposed. The 679. 2 μm × 132. 5μm area size has been achieved in 0. 18 μm 1.8 V 1P6M CMOS technology by the full-custom circuit layout design. The simulation results show that the design way has significantly less area (about 23.52% reduction) and less delay than those of the common saturating MAC based on standard cell library. 展开更多
关键词 multiply-accumulate Booth encoding Wallace tree saturation detection layout design
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Design of adiabatic two's complement multiplier-accumulator based on CTGAL
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作者 Peng-jun WANG Jian XU Shi-yan YING 《Journal of Zhejiang University-Science A(Applied Physics & Engineering)》 SCIE EI CAS CSCD 2009年第2期172-178,共7页
We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multipli... We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two's complement multiplier-accumulator(MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor(CMOS) logic. 展开更多
关键词 CTGAL circuit Adiabatic circuit Booth arithmetic MULTIPLIER Two's complement MAC
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