A modified reduced-order method for RC networks which takes a division-and-conquest strategy is presented.The whole network is partitioned into a set of sub-networks at first,then each of them is reduced by Krylov sub...A modified reduced-order method for RC networks which takes a division-and-conquest strategy is presented.The whole network is partitioned into a set of sub-networks at first,then each of them is reduced by Krylov subspace techniques,and finally all the reduced sub-networks are incorporated together.With some accuracy,this method can reduce the number of both nodes and components of the circuit comparing to the traditional methods which usually only offer a reduced net with less nodes.This can markedly accelerate the sparse-matrix-based simulators whose performance is dominated by the entity of the matrix or the number of components of the circuits.展开更多
An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet ...An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet the delay constraint.A high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look-up table is for buffer delay estimation.The experimental results show that the algorithm can efficiently achieve the trade-offs between number of buffers and delay,and avoid needless power and area cost.The running time is satisfactory.展开更多
文摘A modified reduced-order method for RC networks which takes a division-and-conquest strategy is presented.The whole network is partitioned into a set of sub-networks at first,then each of them is reduced by Krylov subspace techniques,and finally all the reduced sub-networks are incorporated together.With some accuracy,this method can reduce the number of both nodes and components of the circuit comparing to the traditional methods which usually only offer a reduced net with less nodes.This can markedly accelerate the sparse-matrix-based simulators whose performance is dominated by the entity of the matrix or the number of components of the circuits.
文摘An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet the delay constraint.A high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look-up table is for buffer delay estimation.The experimental results show that the algorithm can efficiently achieve the trade-offs between number of buffers and delay,and avoid needless power and area cost.The running time is satisfactory.
