The effects of adjacent metal layers and space between metal lines on the temperature rise of multilevel ULSI interconnect lines are investigated by modeling a three-layer interconnect. The heat dissipation of various...The effects of adjacent metal layers and space between metal lines on the temperature rise of multilevel ULSI interconnect lines are investigated by modeling a three-layer interconnect. The heat dissipation of various metallization technologies concerning the metal and low-k dielectric employment is simulated in detail. The Joule heat generated in the interconnect is transferred mainly through the metal lines in each metal layer and through the path with the smallest thermal resistance in each Ield layer. The temperature rises of Al metallization are approximately pAl/pCu times higher than those of Cu metallization under the same conditions. In addition, a thermal problem in 0.13μm globe interconnects is studied for the worst case, in which there are no metal lines in the lower interconnect layers. Several types of dummy metal heat sinks are investigated and compared with regard to thermal efficiency,influence on parasitic capacitance,and optimal application by combined thermal and electrical simula- tion.展开更多
An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate dela...An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate delay estimation.And heuristic method of buffer insertion is presented to reduce delay.The algorithm is tested by industral circuit case.Experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.展开更多
To obtain a better placement result, a partitioning-based placement algorithm with wirelength prediction called HJ-Pl is presented. A new method is proposed to estimate proximity of interconnects in a netlist, which i...To obtain a better placement result, a partitioning-based placement algorithm with wirelength prediction called HJ-Pl is presented. A new method is proposed to estimate proximity of interconnects in a netlist, which is capable of predicting not only short interconnects but long interconnects accurately. The predicted wirelength is embedded into the partitioning tool of bisection-based global placement, which can guide our placement towards a solution with shorter interconnects. In addition, the timing objective can be handled within the algorithm by minimizing the critical path delay. Experimental results show that, compared to Capol0. 5, mPL6, and NTUplace, HJ-P1 outperforms these placers in terms of wirelength and run time. The improvements in terms of average wirelength over Capo10. 5, mPL6 and NPUplace are 13%, 3%, and 9% with only 19%, 91%, and 99% of their runtime, respectively. By integrating the predicted wirelength-driven clustering into Capo10. 5, the placer is able to reduce average wirelength by 3%. The timing-driven HJ-P1 can reduce the critical path delay by 23%.展开更多
For performance optimization such as placement,interconnect synthesis,and routing, an efficient and accurate interconnect delay metric is critical,even in design tools development like design for yield （DFY） and des...For performance optimization such as placement,interconnect synthesis,and routing, an efficient and accurate interconnect delay metric is critical,even in design tools development like design for yield （DFY） and design for manufacture （DFM）. In the nanometer regime, the recently proposed delay models for RLC interconnects based on statistical probability density function （PDF）interpretation such as PRIMO,H-gamma,WED and RLD bridge the gap between accuracy and efficiency. However, these models always require table look-up when operating. In this paper, a novel delay model based on the Birnbaum-Saunders distribution （BSD） is presented. BSD can accomplish interconnect delay estimation fast and accurately without table look-up operations. Furthermore, it only needs the first two moments to match. Experimental results in 90nm technology show that BSD is robust, easy to implement,efficient,and accurate.展开更多
An algorithm to resolve the coupling effect problem is proposed during the cross point assignment (CPA) stage.In the algorithm,the priority queue concept and the rip-up and reroute strategy are combined to control cro...An algorithm to resolve the coupling effect problem is proposed during the cross point assignment (CPA) stage.In the algorithm,the priority queue concept and the rip-up and reroute strategy are combined to control crosstalk noise caused by interconnect coupling capacitance.First,the nets are arranged into different priority queues according to their weighted sum of their length and criticality.Then,the CPA problem for one queue of nets is translated into a linear assignment problem.After the assignment of one queue of nets,a post-CPA checking routine is performed to check and rip up the net pairs which violate the crosstalk noise constraint and then push them into the next queue to be reassigned.The algorithm is tested by a set of bench mark examples,and the experimental results are promising...展开更多
文摘The effects of adjacent metal layers and space between metal lines on the temperature rise of multilevel ULSI interconnect lines are investigated by modeling a three-layer interconnect. The heat dissipation of various metallization technologies concerning the metal and low-k dielectric employment is simulated in detail. The Joule heat generated in the interconnect is transferred mainly through the metal lines in each metal layer and through the path with the smallest thermal resistance in each Ield layer. The temperature rises of Al metallization are approximately pAl/pCu times higher than those of Cu metallization under the same conditions. In addition, a thermal problem in 0.13μm globe interconnects is studied for the worst case, in which there are no metal lines in the lower interconnect layers. Several types of dummy metal heat sinks are investigated and compared with regard to thermal efficiency,influence on parasitic capacitance,and optimal application by combined thermal and electrical simula- tion.
文摘An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate delay estimation.And heuristic method of buffer insertion is presented to reduce delay.The algorithm is tested by industral circuit case.Experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.
基金The National Key Project of Scientific and Technical Supporting Programs (No.2006BAK07B04)
文摘To obtain a better placement result, a partitioning-based placement algorithm with wirelength prediction called HJ-Pl is presented. A new method is proposed to estimate proximity of interconnects in a netlist, which is capable of predicting not only short interconnects but long interconnects accurately. The predicted wirelength is embedded into the partitioning tool of bisection-based global placement, which can guide our placement towards a solution with shorter interconnects. In addition, the timing objective can be handled within the algorithm by minimizing the critical path delay. Experimental results show that, compared to Capol0. 5, mPL6, and NTUplace, HJ-P1 outperforms these placers in terms of wirelength and run time. The improvements in terms of average wirelength over Capo10. 5, mPL6 and NPUplace are 13%, 3%, and 9% with only 19%, 91%, and 99% of their runtime, respectively. By integrating the predicted wirelength-driven clustering into Capo10. 5, the placer is able to reduce average wirelength by 3%. The timing-driven HJ-P1 can reduce the critical path delay by 23%.
文摘For performance optimization such as placement,interconnect synthesis,and routing, an efficient and accurate interconnect delay metric is critical,even in design tools development like design for yield （DFY） and design for manufacture （DFM）. In the nanometer regime, the recently proposed delay models for RLC interconnects based on statistical probability density function （PDF）interpretation such as PRIMO,H-gamma,WED and RLD bridge the gap between accuracy and efficiency. However, these models always require table look-up when operating. In this paper, a novel delay model based on the Birnbaum-Saunders distribution （BSD） is presented. BSD can accomplish interconnect delay estimation fast and accurately without table look-up operations. Furthermore, it only needs the first two moments to match. Experimental results in 90nm technology show that BSD is robust, easy to implement,efficient,and accurate.
文摘An algorithm to resolve the coupling effect problem is proposed during the cross point assignment (CPA) stage.In the algorithm,the priority queue concept and the rip-up and reroute strategy are combined to control crosstalk noise caused by interconnect coupling capacitance.First,the nets are arranged into different priority queues according to their weighted sum of their length and criticality.Then,the CPA problem for one queue of nets is translated into a linear assignment problem.After the assignment of one queue of nets,a post-CPA checking routine is performed to check and rip up the net pairs which violate the crosstalk noise constraint and then push them into the next queue to be reassigned.The algorithm is tested by a set of bench mark examples,and the experimental results are promising...
