互连线延时和串扰的估算方法

本文综述了集成电路中互连线的延时和串扰的估算方法,分析了各种估算方法的精度和复杂度,同时提出了今后互连线延时和串扰估算所需要解决的新问题。

基于互连线延时的SET脉冲宽度评估模型

研究了互连线延时对单粒子瞬态脉冲效应的影响。研究发现,随着互连线长度的增加,瞬态脉冲首先被展宽,在一定距离后,脉冲宽度衰减为零。基于此研究结果,提出了脉冲宽度随互连线长度变化的数学解析模型。在SMIC 130nm、90nm CMOS工艺下,采用Spice软件对应用该数学解析模型的多种器件进行验证。结果表明,该数学解析模型的计算值与仿真值误差最大为6.09%,最小为0.37%。该模型提高了单粒子瞬态脉冲宽度的评估准确度,可应用于单粒子瞬态脉冲效应的硬件加速模拟。

一种新型FPGA器件延时计算方法

在深亚微米工艺条件下,被广泛使用的Elmore模型明显高估FPGA互连线延时;通过对RC电路冲激响应的研究,提出了采用前3阶矩确立主极点模型来计算FPGA连线延时的方法;该方法实现了计算精度和计算复杂性的折中,理论上证明该方法适用于任何结构RC电路,并且小于Elmore延时;实验表明,该方法对于远端节点估计的延时值和Spice仿真值相差不到1%;应用于商用FPGA,计算所得互连线延时的平均误差小于Elmore模型的三分之一。

A Novel Statistical Delay Model Based on the Birnbaum-Saunders Distribution for RLC Interconnects in 90nm Technologies

For performance optimization such as placement,interconnect synthesis,and routing, an efficient and accurate interconnect delay metric is critical,even in design tools development like design for yield （DFY） and design for manufacture （DFM）. In the nanometer regime, the recently proposed delay models for RLC interconnects based on statistical probability density function （PDF）interpretation such as PRIMO,H-gamma,WED and RLD bridge the gap between accuracy and efficiency. However, these models always require table look-up when operating. In this paper, a novel delay model based on the Birnbaum-Saunders distribution （BSD） is presented. BSD can accomplish interconnect delay estimation fast and accurately without table look-up operations. Furthermore, it only needs the first two moments to match. Experimental results in 90nm technology show that BSD is robust, easy to implement,efficient,and accurate.