An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate dela...An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate delay estimation.And heuristic method of buffer insertion is presented to reduce delay.The algorithm is tested by industral circuit case.Experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.展开更多
文摘An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate delay estimation.And heuristic method of buffer insertion is presented to reduce delay.The algorithm is tested by industral circuit case.Experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.
