信息物理融合电力系统连锁故障中,信息层延时对故障的发展起到推波助澜的作用。为了降低系统故障风险,有必要在故障环境下分析降低延时的方法及其影响。为了缓解信息层信息传输延时和拥塞,首先将软件定义网络（soft defined networks,SD...信息物理融合电力系统连锁故障中,信息层延时对故障的发展起到推波助澜的作用。为了降低系统故障风险,有必要在故障环境下分析降低延时的方法及其影响。为了缓解信息层信息传输延时和拥塞,首先将软件定义网络（soft defined networks,SDN）的构架引入信息物理融合电力系统信息层,提出基于SDN的信息层动态优化路由策略。进而对比了小世界信息层网络和无标度信息层网络下,采用静态路由策略和SDN动态优化路由策略时的传输延时和节点拥堵情况。最后,回到信息物理融合电力系统连锁故障模拟场景,对比讨论了两种路由策略对不同规模连锁故障发展的影响。在小世界信息层网络和无标度信息层网络中,采用SDN动态优化路由策略平衡了不同节点的排队压力,缓解了拥堵程度,降低了最长信息传输延时和平均信息传输延时。连锁故障模拟表明,信息层动态优化路由策略提高了故障中物理电网安全控制的准确性且降低了连锁故障风险。展开更多
Path planning is an important issue for autonomous underwater vehicles （AUVs） traversing an unknown environment such as a sea floor, a jungle, or the outer celestial planets. For this paper, global path planning usi...Path planning is an important issue for autonomous underwater vehicles （AUVs） traversing an unknown environment such as a sea floor, a jungle, or the outer celestial planets. For this paper, global path planning using large-scale chart data was studied, and the principles of ant colony optimization （ACO） were applied. This paper introduced the idea of a visibility graph based on the grid workspace model. It also brought a series of pheromone updating rules for the ACO planning algorithm. The operational steps of the ACO algorithm are proposed as a model for a global path planning method for AUV. To mimic the process of smoothing a planned path, a cutting operator and an insertion-point operator were designed. Simulation results demonstrated that the ACO algorithm is suitable for global path planning. The system has many advantages, including that the operating path of the AUV can be quickly optimized, and it is shorter, safer, and smoother. The prototype system successfully demonstrated the feasibility of the concept, proving it can be applied to surveys of unstructured unmanned environments.展开更多
Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as ...Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge（ENC） is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-（RC）,semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.展开更多
A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） mult...A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.展开更多
s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure re...s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.展开更多
文摘信息物理融合电力系统连锁故障中,信息层延时对故障的发展起到推波助澜的作用。为了降低系统故障风险,有必要在故障环境下分析降低延时的方法及其影响。为了缓解信息层信息传输延时和拥塞,首先将软件定义网络（soft defined networks,SDN）的构架引入信息物理融合电力系统信息层,提出基于SDN的信息层动态优化路由策略。进而对比了小世界信息层网络和无标度信息层网络下,采用静态路由策略和SDN动态优化路由策略时的传输延时和节点拥堵情况。最后,回到信息物理融合电力系统连锁故障模拟场景,对比讨论了两种路由策略对不同规模连锁故障发展的影响。在小世界信息层网络和无标度信息层网络中,采用SDN动态优化路由策略平衡了不同节点的排队压力,缓解了拥堵程度,降低了最长信息传输延时和平均信息传输延时。连锁故障模拟表明,信息层动态优化路由策略提高了故障中物理电网安全控制的准确性且降低了连锁故障风险。
基金Supported by State Key Laboratory of Robotics and System (HIT) under Grant No.SKLRS200706the Heilongjiang Scientific Research Foundation for Postdoctoral Financial Assistance under Grant No.323630221the Project of Harbin Technological Talent Research Foundation under Grant No.RC2006QN009015
文摘Path planning is an important issue for autonomous underwater vehicles （AUVs） traversing an unknown environment such as a sea floor, a jungle, or the outer celestial planets. For this paper, global path planning using large-scale chart data was studied, and the principles of ant colony optimization （ACO） were applied. This paper introduced the idea of a visibility graph based on the grid workspace model. It also brought a series of pheromone updating rules for the ACO planning algorithm. The operational steps of the ACO algorithm are proposed as a model for a global path planning method for AUV. To mimic the process of smoothing a planned path, a cutting operator and an insertion-point operator were designed. Simulation results demonstrated that the ACO algorithm is suitable for global path planning. The system has many advantages, including that the operating path of the AUV can be quickly optimized, and it is shorter, safer, and smoother. The prototype system successfully demonstrated the feasibility of the concept, proving it can be applied to surveys of unstructured unmanned environments.
文摘Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge（ENC） is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-（RC）,semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.
文摘A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.
文摘s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.
