An analog front-end of HF passive RFID transponders compatible with ISO/IEC 18000-3 is presented.Design considerations, especially the power transmission in the RFID transponder, are analyzed. Based on these considera...An analog front-end of HF passive RFID transponders compatible with ISO/IEC 18000-3 is presented.Design considerations, especially the power transmission in the RFID transponder, are analyzed. Based on these considerations,an analog front-end is presented with novel architecture, high power conversion efficiency, low voltage, low power consumption, and high performance in an environment of noise and power fluctuation. The circuit is implemented in a Chartered 0.35μm standard CMOS process. The experimental results show that the chip can satisfy the design target well.展开更多
A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can b...A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.展开更多
To cope with the constraint problem of power consumption and transmission delay in the virtual backbone of wireless sensor network, a distributed connected dominating set （CDS） algorithm with （α,β）-constraints i...To cope with the constraint problem of power consumption and transmission delay in the virtual backbone of wireless sensor network, a distributed connected dominating set （CDS） algorithm with （α,β）-constraints is proposed. Based on the （α, β）-tree concept, a new connected dominating tree with bounded transmission delay problem（CDTT） is defined and a corresponding algorithm is designed to construct a CDT-tree which can trade off limited total power and bounded transmission delay from source to destination nodes. The CDT algorithm consists of two phases： The first phase constructs a maximum independent set（MIS）in a unit disk graph model. The second phase estimates the distance and calculates the transmission power to construct a spanning tree in an undirected graph with different weights for MST and SPF, respectively. The theoretical analysis and simulation results show that the CDT algorithm gives a correct solution to the CDTF problem and forms a virtual backbone with（ α,β）-constraints balancing the requirements of power consumption and transmission delay.展开更多
A novel matching cell circuitry using charge transfer circuit technique for high precision correlation calculation is presented.The cell calculates the absolute value of the difference between two analog input volt...A novel matching cell circuitry using charge transfer circuit technique for high precision correlation calculation is presented.The cell calculates the absolute value of the difference between two analog input voltages and amplifies the result.Amplification gain can be designed by the capacitance size in the cell and threshold voltage mismatch can be canceled automatically,thus high precision operation of the circuit is achieved.The circuit can be operated with low power dissipation of about 12μW at a frequency of 50MHz.Because of its simple structure and small silicon area,the matching cell is suitable to realize the correlation dealing with many template vectors that have many elements in a chip.展开更多
Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementat...Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.展开更多
In this paper,we discuss in detail the basic issue of green design and consider an energy efficiency function as the metric to evaluate green cellular networks.Specifically,we investigate the transmit power required f...In this paper,we discuss in detail the basic issue of green design and consider an energy efficiency function as the metric to evaluate green cellular networks.Specifically,we investigate the transmit power required for an expected transmission capacity and propose a capacity-power formula based on the energy conservation and the Shannon capacity theorem.Two novel definitions of cell interference depth and handoff dynamic model are introduced and the corresponding expression of energy efficiency function is derived.Numerical results show that the energy efficiency function is closely correlated with the transmitted/received power required and the cell radius.Our work provides a useful basis for research and evaluation on green design and technology of cellular networks.展开更多
Currently, the elastic interconnection has realized the high-rate data transmission among data centers(DCs). Thus, the elastic data center network(EDCN) emerged. In EDCNs, it is essential to achieve the virtual networ...Currently, the elastic interconnection has realized the high-rate data transmission among data centers(DCs). Thus, the elastic data center network(EDCN) emerged. In EDCNs, it is essential to achieve the virtual network(VN) embedding, which includes two main components: VM(virtual machine) mapping and VL(virtual link) mapping. In VM mapping, we allocate appropriate servers to hold VMs. While for VL mapping,an optimal substrate path is determined for each virtual lightpath. For the VN embedding in EDCNs, the power efficiency is a significant concern, and some solutions were proposed through sleeping light-duty servers.However, the increasing communication traffic between VMs leads to a serious energy dissipation problem, since it also consumes a great amount of energy on switches even utilizing the energy-efficient optical transmission technique. In this paper, considering load balancing and power-efficient VN embedding, we formulate the problem and design a novel heuristic for EDCNs, with the objective to achieve the power savings of servers and switches. In our solution, VMs are mapped into a single DC or multiple DCs with the short distance between each other, and the servers in the same cluster or adjacent clusters are preferred to hold VMs. Such that, a large amount of servers and switches will become vacant and can go into sleep mode. Simulation results demonstrate that our method performs well in terms of power savings and load balancing. Compared with benchmarks, the improvement ratio of power efficiency is 5%–13%.展开更多
文摘An analog front-end of HF passive RFID transponders compatible with ISO/IEC 18000-3 is presented.Design considerations, especially the power transmission in the RFID transponder, are analyzed. Based on these considerations,an analog front-end is presented with novel architecture, high power conversion efficiency, low voltage, low power consumption, and high performance in an environment of noise and power fluctuation. The circuit is implemented in a Chartered 0.35μm standard CMOS process. The experimental results show that the chip can satisfy the design target well.
文摘A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.
基金Major Program of the National Natural Science Foundation of China (No.70533050)High Technology Research Program ofJiangsu Province(No.BG2007012)+1 种基金China Postdoctoral Science Foundation(No.20070411065)Science Foundation of China University of Mining andTechnology(No.OC080303)
文摘To cope with the constraint problem of power consumption and transmission delay in the virtual backbone of wireless sensor network, a distributed connected dominating set （CDS） algorithm with （α,β）-constraints is proposed. Based on the （α, β）-tree concept, a new connected dominating tree with bounded transmission delay problem（CDTT） is defined and a corresponding algorithm is designed to construct a CDT-tree which can trade off limited total power and bounded transmission delay from source to destination nodes. The CDT algorithm consists of two phases： The first phase constructs a maximum independent set（MIS）in a unit disk graph model. The second phase estimates the distance and calculates the transmission power to construct a spanning tree in an undirected graph with different weights for MST and SPF, respectively. The theoretical analysis and simulation results show that the CDT algorithm gives a correct solution to the CDTF problem and forms a virtual backbone with（ α,β）-constraints balancing the requirements of power consumption and transmission delay.
文摘A novel matching cell circuitry using charge transfer circuit technique for high precision correlation calculation is presented.The cell calculates the absolute value of the difference between two analog input voltages and amplifies the result.Amplification gain can be designed by the capacitance size in the cell and threshold voltage mismatch can be canceled automatically,thus high precision operation of the circuit is achieved.The circuit can be operated with low power dissipation of about 12μW at a frequency of 50MHz.Because of its simple structure and small silicon area,the matching cell is suitable to realize the correlation dealing with many template vectors that have many elements in a chip.
文摘Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.
基金the National Science Foundation of China，the Hi-Tech Research and Development Program of China of Mobile Internet
文摘In this paper,we discuss in detail the basic issue of green design and consider an energy efficiency function as the metric to evaluate green cellular networks.Specifically,we investigate the transmit power required for an expected transmission capacity and propose a capacity-power formula based on the energy conservation and the Shannon capacity theorem.Two novel definitions of cell interference depth and handoff dynamic model are introduced and the corresponding expression of energy efficiency function is derived.Numerical results show that the energy efficiency function is closely correlated with the transmitted/received power required and the cell radius.Our work provides a useful basis for research and evaluation on green design and technology of cellular networks.
基金supported in part by Open Foundation of State Key Laboratory of Information Photonics and Optical Communications (Grant No. IPOC2014B009)Fundamental Research Funds for the Central Universities (Grant Nos. N130817002, N140405005, N150401002)+3 种基金Foundation of the Education Department of Liaoning Province (Grant No. L2014089)National Natural Science Foundation of China (Grant Nos. 61302070, 61401082, 61471109, 61502075)Liaoning Bai Qian Wan Talents ProgramNational High-Level Personnel Special Support Program for Youth Top-Notch Talent
文摘Currently, the elastic interconnection has realized the high-rate data transmission among data centers(DCs). Thus, the elastic data center network(EDCN) emerged. In EDCNs, it is essential to achieve the virtual network(VN) embedding, which includes two main components: VM(virtual machine) mapping and VL(virtual link) mapping. In VM mapping, we allocate appropriate servers to hold VMs. While for VL mapping,an optimal substrate path is determined for each virtual lightpath. For the VN embedding in EDCNs, the power efficiency is a significant concern, and some solutions were proposed through sleeping light-duty servers.However, the increasing communication traffic between VMs leads to a serious energy dissipation problem, since it also consumes a great amount of energy on switches even utilizing the energy-efficient optical transmission technique. In this paper, considering load balancing and power-efficient VN embedding, we formulate the problem and design a novel heuristic for EDCNs, with the objective to achieve the power savings of servers and switches. In our solution, VMs are mapped into a single DC or multiple DCs with the short distance between each other, and the servers in the same cluster or adjacent clusters are preferred to hold VMs. Such that, a large amount of servers and switches will become vacant and can go into sleep mode. Simulation results demonstrate that our method performs well in terms of power savings and load balancing. Compared with benchmarks, the improvement ratio of power efficiency is 5%–13%.
