A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can b...A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.展开更多
A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effect...A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits. A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented. This new static ternary double pass-transistor logic scheme has some favorable properties：the use of standard CMOS process without any modification of the thresholds, a perfectly symmetrical structure,a full logic swing, the maximum possible noise margins, a less complex structure, and no static power consumption. HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.展开更多
Register transfer level mapping (RTLM) algorithm for technology mapping at RT level is presented,which supports current design methodologies using high level design and design reuse.The mapping rules implement a sou...Register transfer level mapping (RTLM) algorithm for technology mapping at RT level is presented,which supports current design methodologies using high level design and design reuse.The mapping rules implement a source ALU using target ALU.The source ALUs and the target ALUs are all represented by the general ALUs and the mapping rules are applied in the algorithm.The mapping rules are described in a table fashion.The graph clustering algorithm is a branch and bound algorithm based on the graph formulation of the mapping algorithm.The mapping algorithm suits well mapping of regularly structured data path.Comparisons are made between the experimental results generated by 1 greedy algorithm and graphclustering algorithm,showing the feasibility of presented algorithm.展开更多
First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked...First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.展开更多
文摘A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.
文摘A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits. A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented. This new static ternary double pass-transistor logic scheme has some favorable properties：the use of standard CMOS process without any modification of the thresholds, a perfectly symmetrical structure,a full logic swing, the maximum possible noise margins, a less complex structure, and no static power consumption. HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.
文摘Register transfer level mapping (RTLM) algorithm for technology mapping at RT level is presented,which supports current design methodologies using high level design and design reuse.The mapping rules implement a source ALU using target ALU.The source ALUs and the target ALUs are all represented by the general ALUs and the mapping rules are applied in the algorithm.The mapping rules are described in a table fashion.The graph clustering algorithm is a branch and bound algorithm based on the graph formulation of the mapping algorithm.The mapping algorithm suits well mapping of regularly structured data path.Comparisons are made between the experimental results generated by 1 greedy algorithm and graphclustering algorithm,showing the feasibility of presented algorithm.
基金Supported by the National Natural Science Foundation of China (No. 60273093)the Natural Science Foundation of Zhejinag Province(No. Y104135) the Student Sci-entific Research Foundation of Ningbo university (No.C38).
文摘First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.
