本系统主要对伪随机序列数据流中的位同步时钟提取和位同步时钟频率测量进行重点设计,采用ALTERA提供的Cyclone V 5CSEMA5F31C6芯片作为主控制器。该系统的创新点在于接收端在传统的数字锁相环(DPLL)的基础上还采用了一种等精度测频法...本系统主要对伪随机序列数据流中的位同步时钟提取和位同步时钟频率测量进行重点设计,采用ALTERA提供的Cyclone V 5CSEMA5F31C6芯片作为主控制器。该系统的创新点在于接收端在传统的数字锁相环(DPLL)的基础上还采用了一种等精度测频法来捕获位同步时钟的频率。通过多项测试,分析并记录数据,结果显示该系统的各项指标均能较好完成设计要求。展开更多
In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
文摘本系统主要对伪随机序列数据流中的位同步时钟提取和位同步时钟频率测量进行重点设计,采用ALTERA提供的Cyclone V 5CSEMA5F31C6芯片作为主控制器。该系统的创新点在于接收端在传统的数字锁相环(DPLL)的基础上还采用了一种等精度测频法来捕获位同步时钟的频率。通过多项测试,分析并记录数据,结果显示该系统的各项指标均能较好完成设计要求。
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
