一种用于电力线载波通信的同步调制解调器

介绍了应用于电力线载波通信的上音频段调制解调器，并详细说明了位锁相电路及 工作原理。

2.5Gb/s/ch 0.18μm CMOS Data Recovery Circuit

A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.

A Novel Digital Transceiver for CT0 Standard

This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth-od. In the transmitter,a fractional-N phase locked loop （PLL） is utilized to realize the continuous phase frequency shift key （CPFSK） modulation,and a 2 Ts raised cosine （2RC） shaping technique is used to reduce the occupied bandwidth. In the receiver,a novel digital method is proposed to demodulate the 2RC CPFSK signal. This chip is fabricated using an SMIC 0.35μm mixed signal CMOS process with a die size of 2mm × 2mm. With an external low noise amplifier （LNA）,the sensitivity of the chip is better than -103dBm.

The Jitter Performance Comparison Between DLL and PLL-Based RF CMOS Oscillators

By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.

A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications

A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.

PLL DEMODULATION TECHNIQUE FOR M-RAY POSITION PHASE SHIFT KEYING

The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation is achieved, as well as carrier recovery and symbol synchronization.Firstly, MPPSK modulation method is briefly introduced.2PPSK's PSD expression is given with its optimization result.Orthogonal Phase Detector(PD) and static threshold are used for the purpose of wider phase range and simplicity in demodulation.The data rate is alterable, which is 4.65 kbps for 2PPSK and 9.3 kbps for 4PPSK in the paper.Then some indicative comparisons in Signal to Noise Ratio Symbol Error Rate(SNR-SER) are made among 2PPSK, 3PPSK and 4PPSK, of which 4PPSK has proved to be optimal in ten slots each symbol conditions.And finally, it is demonstrated by system simulations that lower than 10-4 Symbol Error Rate(SER) performance can be obtained at 13 dB symbol SNR.

Indian Ocean Dipole Response to Global Warming: A Multi-Member Study with CCSM4

Based on a coupled ocean-atmosphere model, the response of the Indian Ocean Dipole (IOD) mode to global warming is investigated with a six member ensemble of simulations for the period 1850-2100. The model can simulate the IOD features rea-listically, including the east-west dipole pattern and the phase locking in boreal autumn. The ensemble analysis suppresses internal variability and isolates the radiative forced response. In response to increasing greenhouse gases, a weakening of the Walker circula-tion leads to the easterly wind anomalies in the equatorial Indian Ocean and the shoaling thermocline in the eastern equatorial Indian Ocean (EEIO), and sea surface temperature and precipitation changes show an IOD-like pattern in the equatorial Indian Ocean. Al-though the thermocline feedback intensifies with shoaling, the interannual variability of the IOD mode surprisingly weakens under global warming. The zonal wind feedback of IOD is found to weaken as well, due to decreased precipitation in the EEIO. Therefore, the atmospheric feedback decreases much more than the oceanic feedback increases, causing the decreased IOD variance in this model.

Measure Synchronization on Symplectic Map

Measure synchronization in coupled Hamiltonian systems is a novel synchronization phenomenon. The measure synchronization on symplectic map is observed numerically, for identical coupled systems with different parameters. We have found the properties of the characteristic frequency and the amplitude of phase locking in regular motion when the measure synchronization of coupled systems is obtained. The relations between the change of the largest Lyapunov exponent and the course of phase desynchronization are also discussed in coupled systems, some useful results are obtained. A new approach is proposed for describing the measure synchronization of coupled systems numerically,which is advantage in judging the measure synchronization, especially for the coupled systems in nonregular region.

A comprehensive simulation of weak-light phase-locking for space-borne gravitational wave antenna

A comprehensive simulation was performed to better understand the impacts and effects of the additional technical noises on weak-light phase-locking for LISA. The result showed that the phase of the slave laser tracked well with the received transmitting light under different noise level, and the locking precision was limited by the phase readout noise when the laser frequency noise and clock jitter noise were removed. This result was then confirmed by a benchtop experimental test. The required LISA noise floor was recovered from the simulation which proved the validity of the simulation program. In order to convert the noise function into real time data with random characteristics, an algorism based on Fourier transform was also invented.

The role of nonlinearities associated with air-sea coupling processes in El Nino's peak-phase locking

We use conditional nonlinear optimal perturbation （CNOP） to investigate the optimal precursory disturbances in the Zebiak- Cane El Nino-Southern Oscillation （ENSO） model. The conditions of the CNOP-type precursors are highly likely to evolve into El Nino events in the Zebiak-Cane model. By exploring the dynamic behaviors of these nonlinear El Nino events caused by the CNOP-type precursors, we find that they, as expected, tend to phase-lock to the annual cycles in the Zebiak-Cane model with the SSTA peak at the end of a calendar year. However, E1 Nino events with CNOPs as initial anomalies in the linearized Zebiak-Cane model are inclined to phase-lock earlier than nonlinear E1 Nino events despite the existence of annual cycles in the model. It is clear that nonlinearities play an important role in El Nino＇s phase-locking. In particular, nonlinear temperature advection increases anomalous zonal SST differences and anomalous westerlies, which weakens anomalous upwelling and acts on the increasing anomalous vertical temperature difference and, as a result, enhances E1 Nino and then delays the peak SSTA. Finally, we demonstrate that nonlinear temperature advection, together with the effect of the annual cycle, causes El Nino events to peak at the end of the calendar year.

A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver

This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well.