参数变化对低功率电弧发动机性能和稳定性的影响

设计了一种功率低于500 W以下的电弧加热发动机的结构和实验系统,采用氮气作为推进剂,系统地测试了该电弧加热发动机在不同工况下的性能参数,并分析了发动机关键尺寸参数和主要工况参数对发动机性能和稳定性的影响,总结得到了稳定工作参数和规律。

A 5mW 1.8V Low Over-Sampling Ratio ΣΔ Modulator with 81dB Dynamic Range

This work demonstrates that the ΣΔ modulator with a low oversampling ratio is a viable option for the high-resolution digitization in a low-voltage environment.Low power dissipation is achieved by designing a low-OSR modulator based on differential cascade architecture,while large signal swing maintained to achieve a high dynamic range in the low-voltage environment.Operating from a voltage supply of 1.8V,the sixth-order cascade modulator at a sampling frequency of 4-MHz with an OSR of 24 achieves a dynamic range of 81dB for a 80-kHz test signal,while dissipating only 5mW.

OPTIMIZATION DESIGN METHOD FOR INPUT IMPEDANCE MATCHING NETWORK OF LOW NOISE AMPLIFIER

According to the theories of optimal noise match and optimal power match, a method for calculating the optimal source impedance of low noise amplifier （LNA） is proposed based on the input reflection coefficient S11. Moreover.with the help of Smith chart, the calculation process is detailed, and the trade-off between the lowest noise figure and the maximum power gain is obtained during the design of LNA input impedance matching network. Based on the Chart 0. 35-μm CMOS process, a traditional cascode LNA circuit is designed and manufactured. Simulation and experimental results have a good agreement with the theoretical analysis, thus proving the correctness of theoretical analysis and the feasibility of the method.

Implementation of a 6 GHz band TDD RF transceiver for the next generation mobile communication system

The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band and the channel bandwidth is up to 100 MHz. It operates in the time division duplex （TDD） mode and supports the multiple-input multipleoutput （MIMO） technique for the international mobile telecommunications （IMT）-advanced systems. The classical superheterodyne scheme is employed to achieve optimal performance. Design issues of the essential components such as low noise amplifier, power amplifier and local oscillators are described in detail. Measurement results show that the maximum linear output power of the RF transceiver is above 23 dBm, and the gain and noise figure of the low noise amplifier is around 24 dB and below 1 dB, respectively. Furthermore, the error vector magnitude （EVM） measurement shows that the performance of the developed RF transceiver is well beyond the requirements of the long term evolution （LTE）-advanced system. With up to 8 x 8 MIMO configuration, the RF transceiver supports more than a 1 Gbit/s data rate in field tests.

Complementary Pass-Transistor Adiabatic Logic Circuit Using Three-Phase Power Supply

A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.

Nested Miller Active-Capacitor Frequency Compensation for Low-Power Three-Stage Amplifiers

A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.

Design of CMOS class-E power amplifier for low power applications

A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.

An enhanced almost blank sub-frame management for efficient elCIC in non-uniform HetNets

A new enhanced inter-cell interference coordination （elCIC） is adopted for managing almost blank sub-frame （ABS）,which jointly exploits the time, frequency and power dimensions to improve the resource utilization. In particular, a non-uniform two tier heterogeneous network （ HetNet） is considered, where the pico cells are located close to the macro cell and the number of users in each pico cell is different. To alleviate the interference caused by the co-channeldeployment,the macro cells employ low power ABS （LP- ABS）, and the resource blocks （RBs） are divided into twoparts during an ABS. One is exclusively reserved for macro cell users ad the other is reserved for pico cell users. Themacro cells are allowed to use different percentages of RBs and different powers for their own transmission during the LP- ABS. The user association,resource allocation,ABS proportion,the frequency band partition parameter and the transmission power of macro cells are considered, aiming at maximizing the proportional fairness utility of the system. An iterative algorithm is also proposed and simulation results demonstrate that the proposed algorithm can improve both the system throughput and user fairness compared with the existing schemes.

Comparative study of effectiveness of different var compensation devices in large-scale power networks

A comparison of the effectiveness of installing reactive power compensators,such as shunt capacitors,static var compensators(SVCs),and static synchronous compensators(STATCOMs),was presented in large-scale power networks.A suitable bus was first identified using modal analysis method.The single shunt capacitor,single SVC,and single STATCOM were installed separately on the most critical bus.The effects of the installation of different devices on power loss reduction,voltage profile improvement,and voltage stability margin enhancement were examined and compared for 57-and 118-bus transmission systems.The comparative study results show that SVC,and STATCOM are expensive compared to shunt capacitor,yet the effect of installing STATCOM is better than SVC and the effect of installing SVC is better than that of shunt capacitor in achieving power loss reduction,voltage profile improvement and voltage stability margin enhancement.

Failure analysis of a kind of low power connector

A kind of low power connector used e.g. in household appliances was partly burned in routine experiment. The heat sources were four paralleled contacts constructed by springs (Sn/CuSn-alloy) in socket and a plug sheet (Ni/Steel) while mating. The contact interfaces were detected by scanning electronic microscope (SEM) and X-ray energy dispersive spectros- copy (XEDS), obvious wear tracks and various contaminants, including element Si, Al, Na, K, S, Cl, O, etc., were found. The contamination degrees on the four paralleled contacts were different, so that the ratio of average contact resistance on the four contacts was about 5:8:3:1. The maximum contact resistance on contacts of the plug sheet reached 28 ?. The main failure rea- sons were fretting and contamination between the contact interfaces. Fretting simulation showed that connection resistance of connectors was raised up, even to ohms level. When the current increased to 5 A, the socket housing was heated and decom- posed. By the thermal analysis, it was estimated that the connector would be burned under the lower current if the current was not evenly distributed on the four paralleled contacts caused by uneven contamination. Improvement methods for connector failure are also discussed.

Low power linear actuator for direct drive electrohydraulic valves

This paper presents a bi-directional permanent-magnet linear actuator for directly driving electrohydraulic valves with low power consumption. Its static and dynamic performances were analyzed using the 2D finite element method,taking into account the nonlinear characterization and the eddy current loss of the magnetic material. The experiment and simulation results agree well and show that the prototype actuator can produce a force of ±100 N with the maximum power being 7 W and has linear characteristics with a positive magnetic stiffness within a stroke of ±1 mm. Its non-linearity is less than 1.5% and the hysteresis less than 1.5%. The actuator's frequency response(-3 dB) of the displacement reaches about 15 Hz,and the most significant factor affecting the dynamic performance is identified as the eddy current loss of the magnetic material.

Energy Recovery Threshold Logic and Power Clock Generation Circuits

Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.

POWER OPTIMIZATION ALGORITHM BASED ON XNOR/OR LOGIC

Based on the investigation of the XNOR/OR logical expression and the propagation al- gorithm of signal probability, a low power synthesis algorithm based on the XNOR/OR logic is pro- posed in this paper. The proposed algorithm has been implemented with C language. Fourteen Mi- croelectronics Center North Carolina (MCNC) benchmarks are tested, and the results show that the proposed algorithm not only significantly reduces the average power consumption up to 27% without area and delay compensations, but also makes the runtime shorter.

Energy Saving and Power Factor Correction for Industrial Plants in Hebron District

Energy efficiency can be improved by reducing the amount of energy that we demand, and by changing our behaviors to reduce the amount of energy that we waste. This scheme manipulates the problem of incremental demand, and low Power Factor （PF） for industrial plants, starting with walk through surveys, data analysis, providing advices to insure personnel involvement, and suggestions of practical circuits to attain the target. Elements of effective energy management program can be configured of management commitment, audit, analysis and implementation. Energy management opportunities can he operational and maintenance strategies, retrofit or modification strategies and new design strategies. The new technique of Power Factor Correction （PFC） that has been designed was the High Active Boost Power Factor Correction Pre-regulator Circuit, which was resulted in single / three phase PFC of about unity, in hand with a regulated output single phase voltage of about 220 VAC.

LOW-POWER LVDS I/O INTERFACE FOR ABOVE 2GB/S-PER-PIN OPERATION

Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.

Novel Design of Low-power Multiplex Differential Voltage Comparators

A novel design of multiplex differential voltage comparators(MDVC) is presented for reducing current and power dissipation. According to the special properties of relational operation and logical operation, parts of the comparators are redundant in some instances, and thus can be turned off. By selecting and switching the current routes, several effective differential pairs are biased by a single tail current stage-by-stage and the redundant comparators are turned off by cutting their tail currents. As a result, the quiescent current and power consumption are greatly decreased. The switching of current is achieved by the input differential pair transistors themselves and hence no extra switches are required. When a MDVC is used in a flash analog-to-digital converter(ADC), its current dissipation is much lower than that of the conventional comparators. This architecture can also be used in window-comparators, maximum or minimum comparators, and comparators for logical operations. The power dissipation in all these cases could be reduced significantly.

Self-Aligned InGaP/GaAs Power HBTswith a Low Bias Voltage

A self aligned InGaP/GaAs power HBTs for L band power amplifier with low bias voltage are described.Base emitter metal self aligning,air bridge,and wafer thinning are used to improve microwave power performance.A power HBT with double size of emitter of (3μm×15μm)×12 is fabricated.When the packaged HBT operates in class AB at a collector bias of 3V,a maximum 23dBm output power with 45% power added efficiency is achieved at 2GHz.The results show that the InGaP/GaAs power HBTs have great potential in mobile communication systems operating at low bias voltage.

A Power Reduction Method for Pilot Channel of LEO Satellite Based on Dynamic Compensation

Since the lower power requirement of code division multiple access(CDMA) than that of other multiple access, the CDMA technology is suitable to be used in low earth orbit(LEO) satellite communication system whose space power is limited due to the small size of satellite. The pilot channel of CDMA technology is very important for earth mobile station(EMS) in LEO system to recover carrier and code, but the power requirement of pilot channel is very higher than that of other channels. In this paper, a power reduction method for pilot channel is proposed. By the new method, the power of pilot channel transmitted from LEO satellite is reduced to a lower level. For improving the signal to noise ratio(SNR) of pilot channel with lower power, coherent integration is employed in EMS at the pre-processing stage. Considering the high dynamic situation of LEO satellite, the long period of time for integration will deteriorate the receiving performance of EMS, therefore, a dynamic compensation module is added to carrier tracking loop against the high dynamic. Meanwhile, the transfer function of the new tracking loop and the condition for steadystate zero error are deduced. Numerical examples are provided to demonstrate effectiveness of the proposed approach.

A low power quadrature up-conversion mixer for WSN application

This paper presents an up-conversion mixer for 2.4GHz wireless sensor networks in 0. 181xm RF complementary metal-oxide semiconductor （CMOS） technology. It is based on a double-balanced Gilbert cell type. With two Gilbert cells it was applied quadrature modulation. Operational ampli- tiers are used in this design to improve the conversion gain under low power consumption. The mixer design is based on 0.18txm RF CMOS process. And the mixer test results indicate that under 1.8V power supply, with input frequency 2.4 - 2.4835GHz, the conversion voltage gain is 1.2 - 2dB. When the output frequency is 2.4GHz, its power gain is -4.46dB, and its input referred 1 dB com- pression point is -11.5dBm and it consumes 1.77mA current.

Analysis and design of sigma-delta interface circuit for quartz flexural pendulum accelerometer

For the high resolution required in a digital interface circuit of an accelerometer used in feeble gravity measurement, a switched-capacitor （SC） sigma-delta modulator （SDM） is proposed. Based on the principle and the topology structure of the SDMs, the influence of oversampling ratio, bits of an internal quantizer and the cascaded structure on weak signal detecting precision is analyzed, and an ideal low-distortion SDM with a second-order 1-bit structure satisfying the high- resolution interface circuit of an accelerometer is designed. With the research on non-idealities of each SDM block in the SC circuit implementation and their impacts on power consumption, the realized parameters of low-power SDMs based on different bandwidths are devised and the power consumption of each SDM is estimated. Time-domain behavioral simulation is explored based on Simulink. The results demonstrate that a 21- bit resolution of the designed SDMs can be achieved on the premise of low power, and the parameters for the circuit implementation can be directed to the transistor-level circuit design.