This paper proposes a cochlear prosthetic system with an implanted digital signal processor （DSP）. This system transmits voice-band signals with a low data rate through the wireless link, free of the data-rate limit...This paper proposes a cochlear prosthetic system with an implanted digital signal processor （DSP）. This system transmits voice-band signals with a low data rate through the wireless link, free of the data-rate limitation and suitable for future development. By optimizing the speech processing algorithm and the DSP hardware design, the implanted DSP manages to execute the continuous interleaved sampling （CIS） algorithm at a clock frequency of 3MHz and a power consumption of only 1.91mW. With an analytic power-transmission efficiency of the wireless inductive link （40%）, the power overhead caused by the implanted DSP is derived as 2.87roW,which is trivial when compared with the power consumption of existing cochlear prosthetic systems （tens of milliwatts）. With the DSP implanted,this new system can.be easily developed into a fully implanted cochlear prosthesis.展开更多
A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signa...A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.展开更多
A LNA with a novel variable gain solution is presented.Compared with the conventional variable gain solutions of LNA,which have more noise degradations when in low gain mode,this solution gives about 25dB variable gai...A LNA with a novel variable gain solution is presented.Compared with the conventional variable gain solutions of LNA,which have more noise degradations when in low gain mode,this solution gives about 25dB variable gain range in 3dB steps,which would cause ultra low noise figure degradation by 0 3～0 5dB.In addition,extra power consumption is not needed by this solution compared with other solutions.展开更多
This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order t...This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order to reduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM is constructed. The optimized LPSR SRAM64K × 32 is used in SoC and the testing method of the LPSR SRAM64K × 32 is also discussed. The SoC design is successfully implemented in the Chartered 90nm CMOS process. The SoC chip occupies 5. 6mm× 5. 6ram of die area and the power dissipation is 1997mW. The test results indicate that LPSR SRAM64K ×32 obtains 17. 301% power savings and the yield of the LPSR SRAM64K × 32s per wafer is improved by 13. 255%.展开更多
In this study, the ethanol extract of pomegranate seed was prepared and its antioxidant activities were investigated. It was found the total phenolic content in the extract was as high as 41.791 mg GAE/g. And the extr...In this study, the ethanol extract of pomegranate seed was prepared and its antioxidant activities were investigated. It was found the total phenolic content in the extract was as high as 41.791 mg GAE/g. And the extract showed high antioxidant activity measured as scavenging of DPPH radicals, hydroxyl radicals. It also exhibited strong antioxidant activity in reducing power and Rancimat test. These results demonstrated Pomegranate seeds could serve as a new source of natural antioxidant.展开更多
This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage cu...This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.展开更多
During the past five decades, the TRIGA reactor Vienna has reached a top place in utilization among low power research reactors. This paper discussed the highlights of the major neutron physics experiments in the fiel...During the past five decades, the TRIGA reactor Vienna has reached a top place in utilization among low power research reactors. This paper discussed the highlights of the major neutron physics experiments in the field of neutron interferometry and ultra-small angle neutron scattering as well as in the field of radiochemistry, education and training and research in the field of nuclear safeguards and nuclear security. Potential further directions of research are outlined where the Atominstitut of Vienna might concentrate in future.展开更多
基金the National Natural Science Foundation of China(No.60475018)~~
文摘This paper proposes a cochlear prosthetic system with an implanted digital signal processor （DSP）. This system transmits voice-band signals with a low data rate through the wireless link, free of the data-rate limitation and suitable for future development. By optimizing the speech processing algorithm and the DSP hardware design, the implanted DSP manages to execute the continuous interleaved sampling （CIS） algorithm at a clock frequency of 3MHz and a power consumption of only 1.91mW. With an analytic power-transmission efficiency of the wireless inductive link （40%）, the power overhead caused by the implanted DSP is derived as 2.87roW,which is trivial when compared with the power consumption of existing cochlear prosthetic systems （tens of milliwatts）. With the DSP implanted,this new system can.be easily developed into a fully implanted cochlear prosthesis.
基金The National Natural Science Foundation of China (No.60772008)the Key Science and Technology Program of Zhejiang Province(No.G2006C13024)
文摘A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.
文摘A LNA with a novel variable gain solution is presented.Compared with the conventional variable gain solutions of LNA,which have more noise degradations when in low gain mode,this solution gives about 25dB variable gain range in 3dB steps,which would cause ultra low noise figure degradation by 0 3～0 5dB.In addition,extra power consumption is not needed by this solution compared with other solutions.
文摘This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order to reduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM is constructed. The optimized LPSR SRAM64K × 32 is used in SoC and the testing method of the LPSR SRAM64K × 32 is also discussed. The SoC design is successfully implemented in the Chartered 90nm CMOS process. The SoC chip occupies 5. 6mm× 5. 6ram of die area and the power dissipation is 1997mW. The test results indicate that LPSR SRAM64K ×32 obtains 17. 301% power savings and the yield of the LPSR SRAM64K × 32s per wafer is improved by 13. 255%.
基金Supported by Foundation for Science and Technology Research Program of Henanprovince(132102110007102102210194)+1 种基金Natural Science Foundation of EducationDepartment in Henan province(2011A550006)Program for Innovative Research Team(in Science and Technology)in University of Henan Province(13IRTSTHN006)
文摘In this study, the ethanol extract of pomegranate seed was prepared and its antioxidant activities were investigated. It was found the total phenolic content in the extract was as high as 41.791 mg GAE/g. And the extract showed high antioxidant activity measured as scavenging of DPPH radicals, hydroxyl radicals. It also exhibited strong antioxidant activity in reducing power and Rancimat test. These results demonstrated Pomegranate seeds could serve as a new source of natural antioxidant.
文摘This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.
文摘During the past five decades, the TRIGA reactor Vienna has reached a top place in utilization among low power research reactors. This paper discussed the highlights of the major neutron physics experiments in the field of neutron interferometry and ultra-small angle neutron scattering as well as in the field of radiochemistry, education and training and research in the field of nuclear safeguards and nuclear security. Potential further directions of research are outlined where the Atominstitut of Vienna might concentrate in future.
