This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter （ADC） fabricated in a 0.25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is reali...This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter （ADC） fabricated in a 0.25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is realized using just four amplifiers with a separate sample-and-hold block. It employs two key techniques： a high bandwidth low-power gain-boosting telescopic amplifiers technique and a low power low offset dynamic comparators technique.The ADC achieves a 8.1 effective number of bits,a maximum differential nonlinearity of a 0.85 least significant bit（LSB）, and maximum integral nonlinearity of 2.2LSB for a 0.5MHz input at full sampling rate. It occupies 1.24mm^2 ,which also includes a bandgap and a voltage reference circuit and dissipates only 59mW.展开更多
A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signa...A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.展开更多
An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit...An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.展开更多
A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performanc...A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.展开更多
Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed wit...Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.展开更多
This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled g...This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.展开更多
文摘This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter （ADC） fabricated in a 0.25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is realized using just four amplifiers with a separate sample-and-hold block. It employs two key techniques： a high bandwidth low-power gain-boosting telescopic amplifiers technique and a low power low offset dynamic comparators technique.The ADC achieves a 8.1 effective number of bits,a maximum differential nonlinearity of a 0.85 least significant bit（LSB）, and maximum integral nonlinearity of 2.2LSB for a 0.5MHz input at full sampling rate. It occupies 1.24mm^2 ,which also includes a bandgap and a voltage reference circuit and dissipates only 59mW.
基金The National Natural Science Foundation of China (No.60772008)the Key Science and Technology Program of Zhejiang Province(No.G2006C13024)
文摘A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.
文摘An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.
文摘A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.
文摘Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.
文摘This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.
