A low power 640×480 OLED-on-silicon chip design that used in microdisplay was presented. A novel pixel circuit was proposed to meet the special requirement of OLED-on-silicon. The novel pixel consists of three tr...A low power 640×480 OLED-on-silicon chip design that used in microdisplay was presented. A novel pixel circuit was proposed to meet the special requirement of OLED-on-silicon. The novel pixel consists of three transistors and one capacitor （3T 1C）. It has simple structure and can effectively reduce the current glitch generated during the AC driving from 55 pA to 7.5 pA, so that it can improve the precision of grayscale of display as well as extend the lifetime of （]）LED material. Except for the pixel array, low power row driver, column driver and other functional modules were also integrated on the chip. Several techniques were adopted to reduce the power consumption and frequency requirement of the chip. Finally, a 16×3×12 resolution chip was fabricated with standard 0.35 μm CMOS process of CSM and the chip can operate correctly.展开更多
A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:...A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.展开更多
Human body communication is proposed as a promising body proximal comanunication tech- nology for body sensor networks. To achieve low power and slmll volume ill the sensor nodes, a Ra-dio Frequency （RF） application...Human body communication is proposed as a promising body proximal comanunication tech- nology for body sensor networks. To achieve low power and slmll volume ill the sensor nodes, a Ra-dio Frequency （RF） application-specific integrated circuit transceiver tbr Human Body Commnunication （HBC） is presented and the characteristics of HBC are investigated. A high data rate On-Off Keying （OOK）/Frequency-Shift Keying （FSK） modulation protocol and an OOK/FSK delrodulator circuit are introduced in this paper, with a data-rate-to-carrier-frequency ratio up to 70%. A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path. In addi-tion, a low power autonmatic-gain-control system is realized using a novel architecture, thereby render-ing the peak detector circuit and loop filter unneces-sary. Finally, the complete chip is fabricated. Simula-tion results suggest receiver sensitivity to be-75 dBm. The transceiver shows an overall power con-smxption of 32 mW when data rate is 5 Mbps, de-livering a P1dB output power of - 30 dBm.展开更多
基金Project(10ZCKFGX00200) supported by the Tianjin Science and Technology Supporting Plan,ChinaProject supported by the Fundamental Research Funds for the Central Universities of China
文摘A low power 640×480 OLED-on-silicon chip design that used in microdisplay was presented. A novel pixel circuit was proposed to meet the special requirement of OLED-on-silicon. The novel pixel consists of three transistors and one capacitor （3T 1C）. It has simple structure and can effectively reduce the current glitch generated during the AC driving from 55 pA to 7.5 pA, so that it can improve the precision of grayscale of display as well as extend the lifetime of （]）LED material. Except for the pixel array, low power row driver, column driver and other functional modules were also integrated on the chip. Several techniques were adopted to reduce the power consumption and frequency requirement of the chip. Finally, a 16×3×12 resolution chip was fabricated with standard 0.35 μm CMOS process of CSM and the chip can operate correctly.
基金Project supported by the Second Stage of Brain Korea 21
文摘A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.
基金This study was supported partially by the Projects of National Natural Science Foundation of China under Crants No. 60932001, No.61072031 the National 863 Program of China un-der Crant No. 2012AA02A604+3 种基金 the National 973 Program of China under Cwant No. 2010CB732606 the Next Generation Communication Technology Major Project of National S＆T un-der Crant No. 2013ZX03005013 the ＂One-hundred Talent＂ and the ＂Low-cost Healthcare＂ Programs of Chinese Academy of Sciences and the Guangdong Innovation Research Team Funds for Low-cost Healthcare and Irrage-Guided Therapy.
文摘Human body communication is proposed as a promising body proximal comanunication tech- nology for body sensor networks. To achieve low power and slmll volume ill the sensor nodes, a Ra-dio Frequency （RF） application-specific integrated circuit transceiver tbr Human Body Commnunication （HBC） is presented and the characteristics of HBC are investigated. A high data rate On-Off Keying （OOK）/Frequency-Shift Keying （FSK） modulation protocol and an OOK/FSK delrodulator circuit are introduced in this paper, with a data-rate-to-carrier-frequency ratio up to 70%. A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path. In addi-tion, a low power autonmatic-gain-control system is realized using a novel architecture, thereby render-ing the peak detector circuit and loop filter unneces-sary. Finally, the complete chip is fabricated. Simula-tion results suggest receiver sensitivity to be-75 dBm. The transceiver shows an overall power con-smxption of 32 mW when data rate is 5 Mbps, de-livering a P1dB output power of - 30 dBm.
