为解决在特殊环境下电子设备噪声超标问题,以某型设备为实例,从设计顶层进行全面考量,在综合均衡散热、电磁兼容等要求的前提下,开展低噪声化的优化设计;以有限元动力学模态仿真、热学流体仿真为设计优化工具,采用理论计算与仿真模拟相...为解决在特殊环境下电子设备噪声超标问题,以某型设备为实例,从设计顶层进行全面考量,在综合均衡散热、电磁兼容等要求的前提下,开展低噪声化的优化设计;以有限元动力学模态仿真、热学流体仿真为设计优化工具,采用理论计算与仿真模拟相结合的手段,从风机选型、风道优化、共振抑制、扰流抑制、减振安装等方面进行了系统性降噪设计与优化,降低了设备的声压级(A声级)5.7 d B,满足了指标要求。通过理论计算与实际测试比较,反向验证了风道优化、共振抑制、扰流抑制、减振安装等优化措施的降噪效果明显,具有一定的指导意义。展开更多
A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signa...A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.展开更多
A LNA with a novel variable gain solution is presented.Compared with the conventional variable gain solutions of LNA,which have more noise degradations when in low gain mode,this solution gives about 25dB variable gai...A LNA with a novel variable gain solution is presented.Compared with the conventional variable gain solutions of LNA,which have more noise degradations when in low gain mode,this solution gives about 25dB variable gain range in 3dB steps,which would cause ultra low noise figure degradation by 0 3～0 5dB.In addition,extra power consumption is not needed by this solution compared with other solutions.展开更多
A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this for...A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5 2GHz CMOS LNA.展开更多
文摘为解决在特殊环境下电子设备噪声超标问题,以某型设备为实例,从设计顶层进行全面考量,在综合均衡散热、电磁兼容等要求的前提下,开展低噪声化的优化设计;以有限元动力学模态仿真、热学流体仿真为设计优化工具,采用理论计算与仿真模拟相结合的手段,从风机选型、风道优化、共振抑制、扰流抑制、减振安装等方面进行了系统性降噪设计与优化,降低了设备的声压级(A声级)5.7 d B,满足了指标要求。通过理论计算与实际测试比较,反向验证了风道优化、共振抑制、扰流抑制、减振安装等优化措施的降噪效果明显,具有一定的指导意义。
基金The National Natural Science Foundation of China (No.60772008)the Key Science and Technology Program of Zhejiang Province(No.G2006C13024)
文摘A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.
文摘A LNA with a novel variable gain solution is presented.Compared with the conventional variable gain solutions of LNA,which have more noise degradations when in low gain mode,this solution gives about 25dB variable gain range in 3dB steps,which would cause ultra low noise figure degradation by 0 3～0 5dB.In addition,extra power consumption is not needed by this solution compared with other solutions.
文摘A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5 2GHz CMOS LNA.
