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大型预焙铝电解槽低电压工艺节能实践 被引量:5
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作者 张天华 黄书文 吴伟 《轻金属》 CSCD 北大核心 2013年第5期31-34,共4页
从"低电压"工艺的概念入手,结合某铝厂大型预焙槽应用实践,指出无论采取锂盐还是普通电解质体系,实施"低电压"工艺中十分重要的环节是适当降低极距。在"高电压"工艺向"低电压"工艺转化过程中,... 从"低电压"工艺的概念入手,结合某铝厂大型预焙槽应用实践,指出无论采取锂盐还是普通电解质体系,实施"低电压"工艺中十分重要的环节是适当降低极距。在"高电压"工艺向"低电压"工艺转化过程中,做好技术参数匹配,以及能量和物料两个平衡的动态控制,找到实现能耗最低极距的"临界点",是"低电压"工艺能否成功的关键。 展开更多
关键词 铝电解槽 低电压工艺 节能 极距 临界点
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1.0 V low voltage CMOS mixer based on voltage control load technique 被引量:1
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作者 韦保林 戴宇杰 +1 位作者 张小兴 吕英杰 《Journal of Central South University》 SCIE EI CAS 2011年第5期1572-1578,共7页
A CMOS active mixer based on voltage control load technique which can operate at 1.0 V supply voltage was proposed, and its operation principle, noise and linearity analysis were also presented. Contrary to the conven... A CMOS active mixer based on voltage control load technique which can operate at 1.0 V supply voltage was proposed, and its operation principle, noise and linearity analysis were also presented. Contrary to the conventional Gilbert-type mixer which is based on RF current-commutating, the load impedance in this proposed mixer is controlled by the LO signal, and it has only two stacked transistors at each branch which is suitable for low voltage applications. The mixer was designed and fabricated in 0.18 tam CMOS process for 2.4 GHz ISM band applications. With an input of 2.44 GHz RF signal and 2.442 GHz LO signal, the measurement specifications of the proposed mixer are: the conversion gain (Gc) is 5.3 dB, the input-referred third-order intercept point (PIIP3) is 4.6 dBm, the input-referred 1 dB compression point (P1dB) is --7.4 dBm, and the single-sideband noise figure (NFSSB) is 21.7 dB. 展开更多
关键词 CMOS active mixer voltage control load technique low voltage
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Low-Power Digital Circuit Design with Triple-Threshold Voltage
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作者 J.B. Kim 《Journal of Energy and Power Engineering》 2010年第9期56-59,共4页
Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low... Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation. 展开更多
关键词 Low-power circuit triple-threshold CMOS circuit carry look-ahead adder very large scale integrated circuit.
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