变压器自身的主要性能参数是短路阻抗。这一性能参数可以决定系统出现短路时变压器自身内部电动力以及短路时整体电流的大小。变压器运行中出现事故的主要原因是变压器绕组变形造成的,它会将变压器的短路阻抗更改,引起间接或直接的变压...变压器自身的主要性能参数是短路阻抗。这一性能参数可以决定系统出现短路时变压器自身内部电动力以及短路时整体电流的大小。变压器运行中出现事故的主要原因是变压器绕组变形造成的,它会将变压器的短路阻抗更改,引起间接或直接的变压器事故或故障。该文通过分析低电压短路阻抗法的应用原理,结合变电站变压器进行实验,实验中变压器为220 k V,在冲击记录超标后研究变压器是否存在绕组变形情况,并针对出现的问题进行诊断。展开更多
New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study o...New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.展开更多
文摘变压器自身的主要性能参数是短路阻抗。这一性能参数可以决定系统出现短路时变压器自身内部电动力以及短路时整体电流的大小。变压器运行中出现事故的主要原因是变压器绕组变形造成的,它会将变压器的短路阻抗更改,引起间接或直接的变压器事故或故障。该文通过分析低电压短路阻抗法的应用原理,结合变电站变压器进行实验,实验中变压器为220 k V,在冲击记录超标后研究变压器是否存在绕组变形情况,并针对出现的问题进行诊断。
文摘New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
