日立制作所开发出了可降低硬盘写入驱动IC耗电量的技术，并在“VLSI symposium on Cursuits”会议上做了技术发表(演讲序号为15-1)。该技术将耗电量由过去的1W左右降低到了380mW，芯片尺寸为1mm×0．96mm，计划用于0．85英寸、1英寸...日立制作所开发出了可降低硬盘写入驱动IC耗电量的技术，并在“VLSI symposium on Cursuits”会议上做了技术发表(演讲序号为15-1)。该技术将耗电量由过去的1W左右降低到了380mW，芯片尺寸为1mm×0．96mm，计划用于0．85英寸、1英寸及1．8英寸微型硬盘。展开更多
Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low...Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.展开更多
文摘Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.
