A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional G...A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFID reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.展开更多
Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixe...Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixed noise of micro arrays effectively. The circuit is simulated in a 0.6 μm/level 7 standard CMOS process, and the simulated results show the output voltage has a good linearity with the transducing current of the micro arrays. This is a novel circuit including four amplifiers sharing a common half-circuit and the noise reducing CDS unit. It could be widely used for micro array biosensors.展开更多
A multi-stage dual replica bit-line delay （MDRBD） technique is proposed for reducing access time by suppressing the sense-amplifier enable （SAE） timing variation of low voltage static randomaccess memory （SRAM） ...A multi-stage dual replica bit-line delay （MDRBD） technique is proposed for reducing access time by suppressing the sense-amplifier enable （SAE） timing variation of low voltage static randomaccess memory （SRAM） applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-fine （RBL） capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology （Taiwan Semiconductor Manufacturing Company, Taiwan）.展开更多
文摘A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFID reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.
基金Natural Science Foundation Project of CQ(2007BB2176)
文摘Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixed noise of micro arrays effectively. The circuit is simulated in a 0.6 μm/level 7 standard CMOS process, and the simulated results show the output voltage has a good linearity with the transducing current of the micro arrays. This is a novel circuit including four amplifiers sharing a common half-circuit and the noise reducing CDS unit. It could be widely used for micro array biosensors.
基金Project supported by the National Natural Science Foundation of China （No. 61474001）
文摘A multi-stage dual replica bit-line delay （MDRBD） technique is proposed for reducing access time by suppressing the sense-amplifier enable （SAE） timing variation of low voltage static randomaccess memory （SRAM） applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-fine （RBL） capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology （Taiwan Semiconductor Manufacturing Company, Taiwan）.
