This paper presents a low voltage, low power RF/analog front-end circuit for passive ultra high frequency （UHF） radio frequency identification （RFID） tags. Temperature compensation is achieved by a reference gener...This paper presents a low voltage, low power RF/analog front-end circuit for passive ultra high frequency （UHF） radio frequency identification （RFID） tags. Temperature compensation is achieved by a reference generator using sub-threshold techniques. The chip maintains a steady system clock in a temperature range from - 40 to 100℃. Some novel building blocks are developed to save system power consumption,including a zero static current power-on reset circuit and a voltage regulator. The RF/analog front-end circuit is implemented with digital base-band and EEPROM to construct a whole tag chip in 0. 18μm CMOS EEPROM technology without Schottcky diodes. Measured results show that the chip has a minimum supply voltage requirement of 0.75V. At this voltage, the total current consumption of the RF/analog frontend circuit is 4.6μA.展开更多
A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:...A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.展开更多
文摘This paper presents a low voltage, low power RF/analog front-end circuit for passive ultra high frequency （UHF） radio frequency identification （RFID） tags. Temperature compensation is achieved by a reference generator using sub-threshold techniques. The chip maintains a steady system clock in a temperature range from - 40 to 100℃. Some novel building blocks are developed to save system power consumption,including a zero static current power-on reset circuit and a voltage regulator. The RF/analog front-end circuit is implemented with digital base-band and EEPROM to construct a whole tag chip in 0. 18μm CMOS EEPROM technology without Schottcky diodes. Measured results show that the chip has a minimum supply voltage requirement of 0.75V. At this voltage, the total current consumption of the RF/analog frontend circuit is 4.6μA.
基金Project supported by the Second Stage of Brain Korea 21
文摘A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.
