提出了一种高温 SOI CMOS电路设计方法—自动体偏置多阈值电压 SOI CMOS(简称 ABB－MT－ SOI CMOS： Auto－ Bulk－ Biased Multi－ Threshold SOI CMOS)电路。文中主要讨论了 ABB－MT－ SOI CMOS电路的结构与工作原理 ,设计与布局等，...提出了一种高温 SOI CMOS电路设计方法—自动体偏置多阈值电压 SOI CMOS(简称 ABB－MT－ SOI CMOS： Auto－ Bulk－ Biased Multi－ Threshold SOI CMOS)电路。文中主要讨论了 ABB－MT－ SOI CMOS电路的结构与工作原理 ,设计与布局等，给出了内部电路电压和电流的模拟结果，并简述了该电路的应用前景。展开更多
A monolithic microwave integrated circuit （MMIC） power amplifier （PA） is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the...A monolithic microwave integrated circuit （MMIC） power amplifier （PA） is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the power supply and temperature, but also compensates deviations caused by the increase in input power. The bias circuit is a current-mirror configuration, and the feedback circuit helps to maintain bias voltage at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit. A shunt capacitor at the base node of the active bias transistor enhances the linearity of the PA. The chip is fabricated in an InGaP/GaAs heterojunction bipolar transistor （HBT） process. Measured results exhibit a 26. 6-dBm output compression point, 33.6% power-added efficiency （PAE） and - 40.2 dBc adjacent channel power ratio （ACPR） for wide-band code division multiple access （W-CDMA） applications.展开更多
文摘提出了一种高温 SOI CMOS电路设计方法—自动体偏置多阈值电压 SOI CMOS(简称 ABB－MT－ SOI CMOS： Auto－ Bulk－ Biased Multi－ Threshold SOI CMOS)电路。文中主要讨论了 ABB－MT－ SOI CMOS电路的结构与工作原理 ,设计与布局等，给出了内部电路电压和电流的模拟结果，并简述了该电路的应用前景。
基金The National High Technology Research and Development Program of China(863 Program)(No.2009AA01Z260)
文摘A monolithic microwave integrated circuit （MMIC） power amplifier （PA） is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the power supply and temperature, but also compensates deviations caused by the increase in input power. The bias circuit is a current-mirror configuration, and the feedback circuit helps to maintain bias voltage at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit. A shunt capacitor at the base node of the active bias transistor enhances the linearity of the PA. The chip is fabricated in an InGaP/GaAs heterojunction bipolar transistor （HBT） process. Measured results exhibit a 26. 6-dBm output compression point, 33.6% power-added efficiency （PAE） and - 40.2 dBc adjacent channel power ratio （ACPR） for wide-band code division multiple access （W-CDMA） applications.
