This paper proposes a cochlear prosthetic system with an implanted digital signal processor （DSP）. This system transmits voice-band signals with a low data rate through the wireless link, free of the data-rate limit...This paper proposes a cochlear prosthetic system with an implanted digital signal processor （DSP）. This system transmits voice-band signals with a low data rate through the wireless link, free of the data-rate limitation and suitable for future development. By optimizing the speech processing algorithm and the DSP hardware design, the implanted DSP manages to execute the continuous interleaved sampling （CIS） algorithm at a clock frequency of 3MHz and a power consumption of only 1.91mW. With an analytic power-transmission efficiency of the wireless inductive link （40%）, the power overhead caused by the implanted DSP is derived as 2.87roW,which is trivial when compared with the power consumption of existing cochlear prosthetic systems （tens of milliwatts）. With the DSP implanted,this new system can.be easily developed into a fully implanted cochlear prosthesis.展开更多
With the continuous increasing of circuit scale, the problem of power consumption is paid much more attention than before, especially in large designs. In this paper, an experience of optimizing the power consumption ...With the continuous increasing of circuit scale, the problem of power consumption is paid much more attention than before, especially in large designs. In this paper, an experience of optimizing the power consumption of the 16-bit datapath in a 32-bit reconfigurable pipelined Digital Signal Processor (DSP) is introduced. By keeping the old input values and preventing the useless switching of the logic blocks on the datapath, the power consumption is much lowered. At the same time, by relocating some logic blocks between different pipeline stages and employing some data forward logics, a better balanced pipeline is achieved to lower the power consumption for conditional computation instructions at very low timing and area costs. The effectivity of these power optimization technologies are proved by the experimental results. Finally, some ideas about how to reduce the power consumption of circuits are proposed, which are very effective and useful in practice designs, especially in pipelined ones.展开更多
This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimizati...This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling （CIS） algorithm is reduced by more than 80 % and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.展开更多
The paper addresses optimization of a performance function which either is optimized via stabilizing and controlling the underlying unknown system or is directly optimized on the basis of its noise-corrupted observati...The paper addresses optimization of a performance function which either is optimized via stabilizing and controlling the underlying unknown system or is directly optimized on the basis of its noise-corrupted observations. For the first case the unknown system is identified and then the indirect adaptive control approach is applied to optimize the performance function. For the second case the stochastic approximation method is used to optimize the objective function, and it appears that a number of problems arising from applications may be reduced to the one solvable by this approach. The paper demonstrates some basic results in the area, but with no intention to give a complete survey.展开更多
基金the National Natural Science Foundation of China(No.60475018)~~
文摘This paper proposes a cochlear prosthetic system with an implanted digital signal processor （DSP）. This system transmits voice-band signals with a low data rate through the wireless link, free of the data-rate limitation and suitable for future development. By optimizing the speech processing algorithm and the DSP hardware design, the implanted DSP manages to execute the continuous interleaved sampling （CIS） algorithm at a clock frequency of 3MHz and a power consumption of only 1.91mW. With an analytic power-transmission efficiency of the wireless inductive link （40%）, the power overhead caused by the implanted DSP is derived as 2.87roW,which is trivial when compared with the power consumption of existing cochlear prosthetic systems （tens of milliwatts）. With the DSP implanted,this new system can.be easily developed into a fully implanted cochlear prosthesis.
文摘With the continuous increasing of circuit scale, the problem of power consumption is paid much more attention than before, especially in large designs. In this paper, an experience of optimizing the power consumption of the 16-bit datapath in a 32-bit reconfigurable pipelined Digital Signal Processor (DSP) is introduced. By keeping the old input values and preventing the useless switching of the logic blocks on the datapath, the power consumption is much lowered. At the same time, by relocating some logic blocks between different pipeline stages and employing some data forward logics, a better balanced pipeline is achieved to lower the power consumption for conditional computation instructions at very low timing and area costs. The effectivity of these power optimization technologies are proved by the experimental results. Finally, some ideas about how to reduce the power consumption of circuits are proposed, which are very effective and useful in practice designs, especially in pipelined ones.
基金Supported by the National Natural Science Foundation of China (No. 60475018)
文摘This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling （CIS） algorithm is reduced by more than 80 % and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.
基金This research is supported by the National Natural Science Foundation of China and the Ministry of Science and Technology of China.
文摘The paper addresses optimization of a performance function which either is optimized via stabilizing and controlling the underlying unknown system or is directly optimized on the basis of its noise-corrupted observations. For the first case the unknown system is identified and then the indirect adaptive control approach is applied to optimize the performance function. For the second case the stochastic approximation method is used to optimize the objective function, and it appears that a number of problems arising from applications may be reduced to the one solvable by this approach. The paper demonstrates some basic results in the area, but with no intention to give a complete survey.
