提出了一种用于高速电荷域流水线模数转换器(Analog-to-Digital Converter,ADC)中的高精度大摆幅电荷传输电路,采用栅压自举技术,克服了现有电荷传输电路中信号摆幅受限的问题。基于该技术,采用0.18μm CMOS工艺,设计并实现了一款14位20...提出了一种用于高速电荷域流水线模数转换器(Analog-to-Digital Converter,ADC)中的高精度大摆幅电荷传输电路,采用栅压自举技术,克服了现有电荷传输电路中信号摆幅受限的问题。基于该技术,采用0.18μm CMOS工艺,设计并实现了一款14位200 MS/s电荷域流水线ADC。在189.9 MHz信号输入和全采样率条件下,信噪比为61.7 d BFS,无杂散动态范围为72.6 d Bc;在1.8 V供电下,ADC整体功耗仅为102 m W。展开更多
A low-power, high-gain circuit for function electrical stimulation （FES） is designed for the microelectronic neural signal regeneration system based on CSMC （CSMC Technologies Corporation） 0. 6μm CMOS （complemen...A low-power, high-gain circuit for function electrical stimulation （FES） is designed for the microelectronic neural signal regeneration system based on CSMC （CSMC Technologies Corporation） 0. 6μm CMOS （complementary metal-oxide-semiconductor transistor） technology. It can be used to stimulate microelectrodes connected with the nerve bundles to regenerate neural signals. This circuit consists of two stages： a full differential folded-cascode amplifier input stage and a complementary class-AB output stage with an overload protection circuit. The rail-to-rail input and output stages are used to ensure a wide range of input and output voltages. The simulation results show that the gain of the circuit is 81 dB; the 3 dB-bandwidth is 295 kHz. The chip occupies a die area of 1.06 mm × 0. 52 mm. The on-wafer measurement results show that under a single supply voltage of ＋ 5 V, the DC power consumption is about 7. 5 mW and the output voltage amplitude is 4. 8 V. The chip can also mn well under single supply voltage of ＋ 3.3 V.展开更多
文摘提出了一种用于高速电荷域流水线模数转换器(Analog-to-Digital Converter,ADC)中的高精度大摆幅电荷传输电路,采用栅压自举技术,克服了现有电荷传输电路中信号摆幅受限的问题。基于该技术,采用0.18μm CMOS工艺,设计并实现了一款14位200 MS/s电荷域流水线ADC。在189.9 MHz信号输入和全采样率条件下,信噪比为61.7 d BFS,无杂散动态范围为72.6 d Bc;在1.8 V供电下,ADC整体功耗仅为102 m W。
基金The National Natural Science Foundation of China(No90377013)
文摘A low-power, high-gain circuit for function electrical stimulation （FES） is designed for the microelectronic neural signal regeneration system based on CSMC （CSMC Technologies Corporation） 0. 6μm CMOS （complementary metal-oxide-semiconductor transistor） technology. It can be used to stimulate microelectrodes connected with the nerve bundles to regenerate neural signals. This circuit consists of two stages： a full differential folded-cascode amplifier input stage and a complementary class-AB output stage with an overload protection circuit. The rail-to-rail input and output stages are used to ensure a wide range of input and output voltages. The simulation results show that the gain of the circuit is 81 dB; the 3 dB-bandwidth is 295 kHz. The chip occupies a die area of 1.06 mm × 0. 52 mm. The on-wafer measurement results show that under a single supply voltage of ＋ 5 V, the DC power consumption is about 7. 5 mW and the output voltage amplitude is 4. 8 V. The chip can also mn well under single supply voltage of ＋ 3.3 V.
