A 12 Gbit/s limiting amplifier using 2 GaAs HBT technology for fiber-optic transmission system

A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving 50 ft transmission lines and a pair of feedback networks for offset cancellation. At a positive supply voltage of 2 V and a negative supply voltage of - 2V, the power dissipation is about 280 mW. The small-signal gain is higher than 46 dB and the input dynamic range is about 40 dB with a constant single-ended output voltage swing of 400 mV. Satisfactory eye-diagrams are obtained at the bit rate of 12 Gbit/s limited by the test set-up. The chip area is 1.15 mm ×0.7 mm.

A signal-summing programmable gain amplifier employing binary-weighted switching and constant-g--_m bias

A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed to vary the current-steering transistors＇ aspect ratio to change their transconductance, and hence, an accurate gain step size of 6dB is achieved. The constant-g_m biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature（ PVT）. P-well NMOS（ Nmetal oxide semiconductor） transistors are utilized to eliminate the influence of back-gate effect which will induce gain error.The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a0.18 μm CMOS（ complementary metal oxide semiconductor）process. The measurement results show a variable gain ranging from 0 to24 dB with a step size of 6 dB and a maximum gain error of 0. 3dB. A constant 3dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point（OIP3） and minimum noise figure（ NF） are20. 9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm^2. The total power consumption is4. 8 mW under a 1. 8 V supply voltage.

Influence of array elements’ consistency on SNR of hydrophone array

The influence of array element’s consistency on the hydrophone array’s signal-to-noise ratio (SNR) is studied. The consistency of array elements means the outputs of all the array’s elements are the same, that is to say, the outputs have the same phase and amplitude when their inputs are the same. The relationship between the SNR and the correlation coefficient of signal and the relationship between the SNR and the correlation coefficient of noise are given. Hydrophone array’s gain with the output of elements’ inconsistent phase and amplitude is analyzed theoretically. When the signal is single-frequency, the gain expression of two-elements array is deduced. Then the gain is calculated when the phase difference is 10° and the amplitude difference is 3 dB. The theoretical analysis is verified through simulation. The simulation results show the variation rule of array’s SNR when the consistency changes: the array SNR gain is greatly affected by the consistency of the elements’ output and the gain decreases as the consistency decreases and the gain may be negative when the amplitude response becomes worse.

UHF power amplifier design in 0.35μm SiGe BiCMOS

A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe BiCMOS process.It was fully integrated excluding the inductors and the output matching network.Under a single 3.3V supply voltage,the off-chip bonding test results indicated that the circuit has a smallsignal gain of more than 24dB,the input and output reflectance are less than- 24dB and-10dB,re-spectively,and the maximal output power is 23.5 dBm.At output power of 23.1 dBm,the PAE(poweradded efficiency)is 30.2%,the IMD2 and IMD3 are less than- 32 dBc and-46 dBc,respectively.The chip size is 1.27mm ×0.9mm.

130 nm CMOS Multi-Stage Synthetic Transmission Line Based Amplifier Beyond 100 GHz

A 130 nm CMOS complementary-conducting-strip transmission line(CCS-TL)based multi-stage amplifier beyond 100 GHz was presented in this paper. Different structural parameters were investigated to achieve higher quality factor for the matching circuits. Moreover, CCS-TL based Marchand balun was implemented to achieve higher output power. The measured small signal gain was higher than 5 d B from 101 GHz to 110 GHz. DC power consumption was 67.2 mW with V_D=1.2 V, and the chip size including contact PADs was 1.12 mm×0.81 mm.

Design of a transversal equalizer for electronic dispersion compensation in optical communication links

A programmable transversal equalizer for electronic dispersion compensation(EDC) in optical fiber communication systems is developed.Based on the SiGe technology with a cut-off frequency of 80 GHz,the equalizer consists of 6 seriesparallel amplifiers as delay units and 7 Gilbert variable gain amplifiers as taps,which ensure that the equalizer can work at the bit rate of 10 Gb/s.With different tap gains,the forward voltage gain of the transversal equalizer varies,which demonstrates that the equalizer has various filtering characteristics such as low pass filtering,band pass filtering,band reject filtering,and notch filtering,so it can effectively simulate the inverse transfer function of dispersive channels in optical communications,and can be used for compensating the inter-symbol interference and other nonlinear problems caused by dispersion.The equalizer(including pads) occupies an area of 0.40 mm × 1.08 mm,and its total power dissipation is 400 mW with 3.3 V power supply.