RELIABLE HYSTERESIS CURRENT CONTROLLED DUAL BUCK HALF BRIDGE INVERTER

A highly efficient and re liable topology-dual buck half bridge inverter (DBI) is introduced. The existenc e of discontinuous conduction mode (DCM) operation state requires the bias of in du ctor current for DBI implemented with linear controllers like ramp comparison SP WM (RCSPWM) controllers. A novel operation scheme for DBI and a hysteresis curre nt controlled dual buck half bridge inverter (HCDBI) are proposed. The bias curr ent required by RCSPWM DBI is eliminated and conduction losses are dramatically reduced. HCDBI has greatly improved the modulation performance in DCM region for the benefit of its excellent command tracking capability. The operational schem e and control strategy are presented. Power losses of the conventional half brid ge inverter (CHBI) and HCDBI are compared with mathematical computation, and exp erimental verification is also executed. Both calculational and experimental res ults verify that HCDBI has a superior switching performance over CHBI. Its exce llent high frequency operational capacity provides another access to realize high fre quency operation of inverters.

Optimal design of APD biasing circuit

This paper proposes a control method for avalanche photodiode(APD) reverse bias with temperature compensation and load resistance compensation. The influence of background light and load resistance on APD detection circuit is analyzed in detail. A theoretical model of temperature compensation and load resistance compensation is established,which is used for APD biasing circuit designing. It is predicted that this control method is especially suitable for LD laser range finder used on vehicles. Experimental results confirm that the design proposed in this paper can considerablely improve the performance of range finder.

CMOS Automatic Gain Control Circuit with DC Offset Cancellation for FM/cw Ladar

This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.

A 3GHz Low-Power and Low-Phase-Noise LC VCO with a Self-Biasing Current Source

A fully integrated 3GHz low-power and low-phase-noise voltage-controlled oscillator （VCO） with a self-biasing current source was implemented in a standard 0.18μm CMOS process. A trade-off between noise and power was realized through the optimization of the improved current source. The VCO can be tuned from 2.83 to 3.25GHz with a 13.8% tuning range. The measured phase noise at 1MHz offset is -111dBc/Hz at a frequency of 3.22GHz while the core circuit draws less than 2mA from a 1.8V supply voltage. These results make the circuit suitable for a 5GHz wireless local area network （WLAN） receiver and 3.4 to 3.6GHz world interoperability for microwave access （WiMAX） application.