An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit...An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.展开更多
The first domestic 1×10^6rad（Si） total dose hardened 1.2μm partially depleted silicon-on-insulator （PDSOI） 64k SRAM fabricated in SIMOX is demonstrated.The address access time is independent of temperature f...The first domestic 1×10^6rad（Si） total dose hardened 1.2μm partially depleted silicon-on-insulator （PDSOI） 64k SRAM fabricated in SIMOX is demonstrated.The address access time is independent of temperature from -55 to 125℃ and independent of radiation up to 1×10^6rad（Si） for the supply voltage VDD.The standby current is 0.65μA before the total dose of radiation and is only 0.80mA after radiation exposure,which is much better than the specified 10mA.The operating power supply current is 33.0mA before and only 38.1mA afterward,which is much better than the specified 100mA.展开更多
A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing....A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.展开更多
The AgTCNQ thin-film was prepared by vacuum vapor co-deposition and characterized by infrared spectral analysis,and then a uniform AgTCNQ （TCNQ-- 7,7,8,8-tetracyanoquinodimethane） thin-film layer was sandwiched in a...The AgTCNQ thin-film was prepared by vacuum vapor co-deposition and characterized by infrared spectral analysis,and then a uniform AgTCNQ （TCNQ-- 7,7,8,8-tetracyanoquinodimethane） thin-film layer was sandwiched in a Ti/AgTCNQ/Ati crossbar structure array as organic bistable devices （OBD）.A reversible and reproducible memory switching property,caused by intermolecular charge transfer （CT） in the AgTCNQ thin-film, was observed in the organic bista- ble devices. The positive threshold voltage from the high impedance state to the low impedance was about 3.8-5V, with the reverse phenomenon occurring at a negative voltage of - 3.5- - 4. 4V,lower than that with a CuTCNQ active layer. The crossbar array of OBDs with AgTCNQ is promising for nonvolatile organic memory applications.展开更多
To ensure revulsive driving of intelligent vehicles at intersections, a method is presented to detect and recognize the traffic lights. First, the stabling siding at intersections is detected by applying Hough transfo...To ensure revulsive driving of intelligent vehicles at intersections, a method is presented to detect and recognize the traffic lights. First, the stabling siding at intersections is detected by applying Hough transformation. Then, the colors of traffic lights are detected with color space transformation. Finally, self-associative memory is used to recognize the countdown characters of the traffic lights. Test results at 20 real intersections show that the ratio of correct stabling siding recognition reaches up to 90%;and the ratios of recognition of traffic lights and divided characters are 85% and 97%, respectively. The research proves that the method is efficient for the detection of stabling siding and is robust enough to recognize the characters from images with noise and broken edges.展开更多
To improve I/O speed and system performance of network storage devices, a special storage server that is an iSCSI-based network-attached storage server (iSCSI-based network-attached storage server, for short iNAS) is ...To improve I/O speed and system performance of network storage devices, a special storage server that is an iSCSI-based network-attached storage server (iSCSI-based network-attached storage server, for short iNAS) is designed. The iNAS can provide both the file I/O and the block I/O services by an iSCSI module, and it converges with the NAS and the SAN (storage area network). The iNAS improves the I/O speed by the direct data access (zero copy) between the RAID (redundant array of inexpensive disks) controller and the user-level memory. The iNAS integrates the multi-RAID for a single storage pool by a multi-stage stripping device driver, and it implements the storage virtualization. In the experiments, the iNAS has ultra-high-throughput for both the file I/O requests and the block I/O requests.展开更多
Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure ...Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure which only requires an additional masking step to form the novel structure in the channel.For the cell of the 1 2μm gate length,the programming speed of 43μs under the measuring condition of V g=15V, V d=5V,and the erasing time of 24ms under V g=-5V, V s=8V are obtained.The programming speed is faster than that of the conventional planar cell structure.This superior programming speed makes it suitable for high speed application.展开更多
Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,hig...Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,high efficiency for injection,and lower working voltage are obtained.Simulation and analysis for the proposed SCDI structure device are done and an optimization scheme to improve the utmost performance of SCDI device is given...展开更多
Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed ...Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed of SCDI device is 42μs.Under the condition of V g=-8V, V s=8V,the erasing speed is 24ms.Compared with the same size of conventional flash memory device whose corresponding parameters are 500μs and 24ms,respectively,the performance of SCDI device is remarkably improved.During manufacturing of SCDI device,the key technologies are to make the shallow step with appropriate depth and angle,along with eliminating the etch damage during the process of Si 3N 4 spacer.展开更多
High order bidirectional associative memory (HOBAM) by Tai et al is extension to Kosko′s bidirectional associative memory(BAM). It not only possesses merits of the BAM, but also relaxes the continuity assumption for...High order bidirectional associative memory (HOBAM) by Tai et al is extension to Kosko′s bidirectional associative memory(BAM). It not only possesses merits of the BAM, but also relaxes the continuity assumption for reliable recalls and significantly improves the storage capacity and error correcting capability of the BAM. However, Tai′s performance analysis for the HOBAM is only limited in the computer simulations, in the other words, they did not give a theoretical analysis result. This paper fills the blank and gives a theoretical proof for HOBAM′s stability and storage capacity analysis so that the system can theoretically ensure all the training pattern pairs to become its stable points.展开更多
For sparse storage and quick access to projection matrix based on vector type, this paper proposes a method to solve the problems of the repetitive computation of projection coefficient, the large space occupation and...For sparse storage and quick access to projection matrix based on vector type, this paper proposes a method to solve the problems of the repetitive computation of projection coefficient, the large space occupation and low retrieval efficiency of projection matrix in iterative reconstruction algorithms, which calculates only once the projection coefficient and stores the data sparsely in binary format based on the variable size of library vector type. In the iterative reconstruction process, these binary files are accessed iteratively and the vector type is used to quickly obtain projection coefficients of each ray. The results of the experiments show that the method reduces the memory space occupation of the projection matrix and the computation of projection coefficient in iterative process, and accelerates the reconstruction speed.展开更多
Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed wit...Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.展开更多
文摘An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.
文摘The first domestic 1×10^6rad（Si） total dose hardened 1.2μm partially depleted silicon-on-insulator （PDSOI） 64k SRAM fabricated in SIMOX is demonstrated.The address access time is independent of temperature from -55 to 125℃ and independent of radiation up to 1×10^6rad（Si） for the supply voltage VDD.The standby current is 0.65μA before the total dose of radiation and is only 0.80mA after radiation exposure,which is much better than the specified 10mA.The operating power supply current is 33.0mA before and only 38.1mA afterward,which is much better than the specified 100mA.
文摘A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.
文摘The AgTCNQ thin-film was prepared by vacuum vapor co-deposition and characterized by infrared spectral analysis,and then a uniform AgTCNQ （TCNQ-- 7,7,8,8-tetracyanoquinodimethane） thin-film layer was sandwiched in a Ti/AgTCNQ/Ati crossbar structure array as organic bistable devices （OBD）.A reversible and reproducible memory switching property,caused by intermolecular charge transfer （CT） in the AgTCNQ thin-film, was observed in the organic bista- ble devices. The positive threshold voltage from the high impedance state to the low impedance was about 3.8-5V, with the reverse phenomenon occurring at a negative voltage of - 3.5- - 4. 4V,lower than that with a CuTCNQ active layer. The crossbar array of OBDs with AgTCNQ is promising for nonvolatile organic memory applications.
基金The Cultivation Fund of the Key Scientific and Technical Innovation Project of Higher Education of Ministry of Education (No.705020)
文摘To ensure revulsive driving of intelligent vehicles at intersections, a method is presented to detect and recognize the traffic lights. First, the stabling siding at intersections is detected by applying Hough transformation. Then, the colors of traffic lights are detected with color space transformation. Finally, self-associative memory is used to recognize the countdown characters of the traffic lights. Test results at 20 real intersections show that the ratio of correct stabling siding recognition reaches up to 90%;and the ratios of recognition of traffic lights and divided characters are 85% and 97%, respectively. The research proves that the method is efficient for the detection of stabling siding and is robust enough to recognize the characters from images with noise and broken edges.
文摘To improve I/O speed and system performance of network storage devices, a special storage server that is an iSCSI-based network-attached storage server (iSCSI-based network-attached storage server, for short iNAS) is designed. The iNAS can provide both the file I/O and the block I/O services by an iSCSI module, and it converges with the NAS and the SAN (storage area network). The iNAS improves the I/O speed by the direct data access (zero copy) between the RAID (redundant array of inexpensive disks) controller and the user-level memory. The iNAS integrates the multi-RAID for a single storage pool by a multi-stage stripping device driver, and it implements the storage virtualization. In the experiments, the iNAS has ultra-high-throughput for both the file I/O requests and the block I/O requests.
文摘Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure which only requires an additional masking step to form the novel structure in the channel.For the cell of the 1 2μm gate length,the programming speed of 43μs under the measuring condition of V g=15V, V d=5V,and the erasing time of 24ms under V g=-5V, V s=8V are obtained.The programming speed is faster than that of the conventional planar cell structure.This superior programming speed makes it suitable for high speed application.
文摘Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,high efficiency for injection,and lower working voltage are obtained.Simulation and analysis for the proposed SCDI structure device are done and an optimization scheme to improve the utmost performance of SCDI device is given...
文摘Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed of SCDI device is 42μs.Under the condition of V g=-8V, V s=8V,the erasing speed is 24ms.Compared with the same size of conventional flash memory device whose corresponding parameters are 500μs and 24ms,respectively,the performance of SCDI device is remarkably improved.During manufacturing of SCDI device,the key technologies are to make the shallow step with appropriate depth and angle,along with eliminating the etch damage during the process of Si 3N 4 spacer.
文摘High order bidirectional associative memory (HOBAM) by Tai et al is extension to Kosko′s bidirectional associative memory(BAM). It not only possesses merits of the BAM, but also relaxes the continuity assumption for reliable recalls and significantly improves the storage capacity and error correcting capability of the BAM. However, Tai′s performance analysis for the HOBAM is only limited in the computer simulations, in the other words, they did not give a theoretical analysis result. This paper fills the blank and gives a theoretical proof for HOBAM′s stability and storage capacity analysis so that the system can theoretically ensure all the training pattern pairs to become its stable points.
基金National Natural Science Foundation of China(No.6171177)
文摘For sparse storage and quick access to projection matrix based on vector type, this paper proposes a method to solve the problems of the repetitive computation of projection coefficient, the large space occupation and low retrieval efficiency of projection matrix in iterative reconstruction algorithms, which calculates only once the projection coefficient and stores the data sparsely in binary format based on the variable size of library vector type. In the iterative reconstruction process, these binary files are accessed iteratively and the vector type is used to quickly obtain projection coefficients of each ray. The results of the experiments show that the method reduces the memory space occupation of the projection matrix and the computation of projection coefficient in iterative process, and accelerates the reconstruction speed.
文摘Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.
