Helper-thread of a task can hide the memory access time of irregular data on the chip muhi-core processor （CMP）. For constructing a compiler that effectively supports the helper-thread of a task in the multi-core sc...Helper-thread of a task can hide the memory access time of irregular data on the chip muhi-core processor （CMP）. For constructing a compiler that effectively supports the helper-thread of a task in the multi-core scenario based on the last level shared cache, this paper studies its performance stable condi- tions. Unfortunately, there is no existing model that allows extensive investigation of the impact of stable conditions, we present the base of pre-computation that is formalized by our degraded task-pair 〈 T, T＇ 〉 with the helper-thread, and its stable conditions are analyzed. Finally, a novel performance model and a constructing method of pre-computation based on our positive degraded task-pair are proposed. The efficient results are shown by our experiments. If we further exploit memory level parallelism （MLP） for our task-pair, the task-pair 〈 T, T＇ 〉 can reach better performance.展开更多
Dynamic random access memory(DRAM) is facing the challenge of technology scaling. The decreasing feature size makes it harder to make DRAM cells which can keep the current data-holding time. When DRAM cells cannot hol...Dynamic random access memory(DRAM) is facing the challenge of technology scaling. The decreasing feature size makes it harder to make DRAM cells which can keep the current data-holding time. When DRAM cells cannot hold data for a long time, DRAM chips need a more frequent refreshing operation. Therefore, in the near future, time and energy cost on DRAM refreshing will be no longer trivial. In this paper, we propose DRAM Error Correction Pointer(ECP), an error-correction-manner framework, to reduce DRAM refreshes without data loss. We exploit the non-uniform feature of DRAM cells with respect to the data retention time. Compared with the conventional refreshing mechanisms, which refresh DRAM chips by the retention time of the leakiest cells, we refresh the chips much fewer times, and treat the not-in-time refreshed cells as fault elements. We use the structure of ECP as a fault tolerant element. By recording the data which are supposed to be written into the leaky cells in our DRAM-ECP structures, DRAM-ECP can significantly decrease refreshing frequency. When these data are to be read out, DRAM-ECP retrieves the data stored in ECPs and covers them to the corresponding position in the data row. Our experiments show that DRAM-ECP can reduce over 70%refreshing operations than the current refreshing mechanism and also get significant energy saving.展开更多
文摘Helper-thread of a task can hide the memory access time of irregular data on the chip muhi-core processor （CMP）. For constructing a compiler that effectively supports the helper-thread of a task in the multi-core scenario based on the last level shared cache, this paper studies its performance stable condi- tions. Unfortunately, there is no existing model that allows extensive investigation of the impact of stable conditions, we present the base of pre-computation that is formalized by our degraded task-pair 〈 T, T＇ 〉 with the helper-thread, and its stable conditions are analyzed. Finally, a novel performance model and a constructing method of pre-computation based on our positive degraded task-pair are proposed. The efficient results are shown by our experiments. If we further exploit memory level parallelism （MLP） for our task-pair, the task-pair 〈 T, T＇ 〉 can reach better performance.
基金supported by National High-tech R&D Program of China(863 Program)(Grant No.2012AA01A3-02)National Natural Science Foundation of China(Grant Nos.61133004+2 种基金61361126011)State Key Laboratory of Software Development Environment(Grant No.SKLSDE-2013ZX-22)Open Project Program of the State Key Laboratory of Mathematical Engineering and Advanced Computing
文摘Dynamic random access memory(DRAM) is facing the challenge of technology scaling. The decreasing feature size makes it harder to make DRAM cells which can keep the current data-holding time. When DRAM cells cannot hold data for a long time, DRAM chips need a more frequent refreshing operation. Therefore, in the near future, time and energy cost on DRAM refreshing will be no longer trivial. In this paper, we propose DRAM Error Correction Pointer(ECP), an error-correction-manner framework, to reduce DRAM refreshes without data loss. We exploit the non-uniform feature of DRAM cells with respect to the data retention time. Compared with the conventional refreshing mechanisms, which refresh DRAM chips by the retention time of the leakiest cells, we refresh the chips much fewer times, and treat the not-in-time refreshed cells as fault elements. We use the structure of ECP as a fault tolerant element. By recording the data which are supposed to be written into the leaky cells in our DRAM-ECP structures, DRAM-ECP can significantly decrease refreshing frequency. When these data are to be read out, DRAM-ECP retrieves the data stored in ECPs and covers them to the corresponding position in the data row. Our experiments show that DRAM-ECP can reduce over 70%refreshing operations than the current refreshing mechanism and also get significant energy saving.
