2.5 Gbit/s monolithic integrated circuits （ICs） for optical fiber transmitter and receiver in 0.35 μm CMOS （complementary metal-oxide-semiconductor transistor） process are presented. The transmitter, which includ...2.5 Gbit/s monolithic integrated circuits （ICs） for optical fiber transmitter and receiver in 0.35 μm CMOS （complementary metal-oxide-semiconductor transistor） process are presented. The transmitter, which includes a 4： 1 multiplexer and a laser diode driver （LDD）, has four 622 Mbit/s random signals as its inputs and gets a 2.5 Gbit/s driving signal as its output; the receiver detects a 2.5 Gbit/s random signal and gets four 622 Mbit/s signals at the output. The main circuits include a trans-impedance amplifier （TIA）, a limiting amplifier, a clock and data recovery （CDR） unit, and a 1： 4 demultiplexer （DEMUX）. Test results prove the logic functions of the transmitter to be right, and the 10% to 90% rise and fall times of transmitter＇s output data eye diagram are 211.1 ps and 200 ps, respectively. The sensitivity of the receiver is measured to be better than 20 mV. The root mean square jitter of the DEMUX＇s output data is 15.6 ps and that of the clock after 1： 4 frequency dividing is 1.9 ps. Two chips are both applicable to 2.5 Gbit/s optical fiber communication systems.展开更多
A novel transmitter to generate a dark RZ signal with tunable duty cycle and extinction ratio is proposed, by modifying the process of preceding, modulating and coding, A dark RZ signal is generated simply by using on...A novel transmitter to generate a dark RZ signal with tunable duty cycle and extinction ratio is proposed, by modifying the process of preceding, modulating and coding, A dark RZ signal is generated simply by using one dual-arm Mach-Zehnder LiNbO3 modulator. We demonstrate experimentally that this optical dark RZ signal can be directly measured by a conventional binary intensity modulation direct detection （IM-DD） receiver. When different values of duty cycles at 2.5 Gbit/s are adjusted, the experimental results show different BER curves and eye diagrams of the optical dark RZ signal.展开更多
This paper presents an innovative switched-mode auto gain control （AGC） circuit with internally created reset module for DC-10Mb/s burst-mode unbalanced （BMU） optical data transmission. Conventional AGC circuit is...This paper presents an innovative switched-mode auto gain control （AGC） circuit with internally created reset module for DC-10Mb/s burst-mode unbalanced （BMU） optical data transmission. Conventional AGC circuit is inappropriate for BMU data transmission because it is based on average level detection and requires considerable time to settle on a predefined gain. Therefore, we adopt a fast switched-mode AGC based on peak level detection. After the gain is adjusted, the peak level detectors need to re-detect the peak level of the input signal. Thus, we develop an internally created reset module. This AGC with reset module exhibits a fast operation and achieves an adjusted stable gain within one-bit, avoiding any bit loss up to 10Mb/s data rate. During power-up, the peak level detectors possibly hold an uncertain level resulting in the bit-errors. We propose a power-up reset circuit to solve this problem. Designed in a 0.5μm CMOS technology, the circuit achieves an optical sensitivity of better than -30dBm and a wide dynamic range of over 30dB with a power dissipation of only 30 mW from a 5V supply.展开更多
基金The National High Technology Research and Develop-ment Program of China (863 Program) (No.2001AA312010).
文摘2.5 Gbit/s monolithic integrated circuits （ICs） for optical fiber transmitter and receiver in 0.35 μm CMOS （complementary metal-oxide-semiconductor transistor） process are presented. The transmitter, which includes a 4： 1 multiplexer and a laser diode driver （LDD）, has four 622 Mbit/s random signals as its inputs and gets a 2.5 Gbit/s driving signal as its output; the receiver detects a 2.5 Gbit/s random signal and gets four 622 Mbit/s signals at the output. The main circuits include a trans-impedance amplifier （TIA）, a limiting amplifier, a clock and data recovery （CDR） unit, and a 1： 4 demultiplexer （DEMUX）. Test results prove the logic functions of the transmitter to be right, and the 10% to 90% rise and fall times of transmitter＇s output data eye diagram are 211.1 ps and 200 ps, respectively. The sensitivity of the receiver is measured to be better than 20 mV. The root mean square jitter of the DEMUX＇s output data is 15.6 ps and that of the clock after 1： 4 frequency dividing is 1.9 ps. Two chips are both applicable to 2.5 Gbit/s optical fiber communication systems.
基金This work is supported by the National Natural Science Founda-tion of China (Grant No.10576012)the Specialized ResearchFund for the Doctoral Program of Higher Education of China(Grant No.20040532005)
文摘A novel transmitter to generate a dark RZ signal with tunable duty cycle and extinction ratio is proposed, by modifying the process of preceding, modulating and coding, A dark RZ signal is generated simply by using one dual-arm Mach-Zehnder LiNbO3 modulator. We demonstrate experimentally that this optical dark RZ signal can be directly measured by a conventional binary intensity modulation direct detection （IM-DD） receiver. When different values of duty cycles at 2.5 Gbit/s are adjusted, the experimental results show different BER curves and eye diagrams of the optical dark RZ signal.
基金Supported by the Natural Science Foundation of Jiangsu Province （ BK2010411 ） and the National International Cooperation Project of China-Korea （2011DFA11310）.
文摘This paper presents an innovative switched-mode auto gain control （AGC） circuit with internally created reset module for DC-10Mb/s burst-mode unbalanced （BMU） optical data transmission. Conventional AGC circuit is inappropriate for BMU data transmission because it is based on average level detection and requires considerable time to settle on a predefined gain. Therefore, we adopt a fast switched-mode AGC based on peak level detection. After the gain is adjusted, the peak level detectors need to re-detect the peak level of the input signal. Thus, we develop an internally created reset module. This AGC with reset module exhibits a fast operation and achieves an adjusted stable gain within one-bit, avoiding any bit loss up to 10Mb/s data rate. During power-up, the peak level detectors possibly hold an uncertain level resulting in the bit-errors. We propose a power-up reset circuit to solve this problem. Designed in a 0.5μm CMOS technology, the circuit achieves an optical sensitivity of better than -30dBm and a wide dynamic range of over 30dB with a power dissipation of only 30 mW from a 5V supply.
