2.5 Gbit/s monolithic integrated circuits （ICs） for optical fiber transmitter and receiver in 0.35 μm CMOS （complementary metal-oxide-semiconductor transistor） process are presented. The transmitter, which includ...2.5 Gbit/s monolithic integrated circuits （ICs） for optical fiber transmitter and receiver in 0.35 μm CMOS （complementary metal-oxide-semiconductor transistor） process are presented. The transmitter, which includes a 4： 1 multiplexer and a laser diode driver （LDD）, has four 622 Mbit/s random signals as its inputs and gets a 2.5 Gbit/s driving signal as its output; the receiver detects a 2.5 Gbit/s random signal and gets four 622 Mbit/s signals at the output. The main circuits include a trans-impedance amplifier （TIA）, a limiting amplifier, a clock and data recovery （CDR） unit, and a 1： 4 demultiplexer （DEMUX）. Test results prove the logic functions of the transmitter to be right, and the 10% to 90% rise and fall times of transmitter＇s output data eye diagram are 211.1 ps and 200 ps, respectively. The sensitivity of the receiver is measured to be better than 20 mV. The root mean square jitter of the DEMUX＇s output data is 15.6 ps and that of the clock after 1： 4 frequency dividing is 1.9 ps. Two chips are both applicable to 2.5 Gbit/s optical fiber communication systems.展开更多
基金The National High Technology Research and Develop-ment Program of China (863 Program) (No.2001AA312010).
文摘2.5 Gbit/s monolithic integrated circuits （ICs） for optical fiber transmitter and receiver in 0.35 μm CMOS （complementary metal-oxide-semiconductor transistor） process are presented. The transmitter, which includes a 4： 1 multiplexer and a laser diode driver （LDD）, has four 622 Mbit/s random signals as its inputs and gets a 2.5 Gbit/s driving signal as its output; the receiver detects a 2.5 Gbit/s random signal and gets four 622 Mbit/s signals at the output. The main circuits include a trans-impedance amplifier （TIA）, a limiting amplifier, a clock and data recovery （CDR） unit, and a 1： 4 demultiplexer （DEMUX）. Test results prove the logic functions of the transmitter to be right, and the 10% to 90% rise and fall times of transmitter＇s output data eye diagram are 211.1 ps and 200 ps, respectively. The sensitivity of the receiver is measured to be better than 20 mV. The root mean square jitter of the DEMUX＇s output data is 15.6 ps and that of the clock after 1： 4 frequency dividing is 1.9 ps. Two chips are both applicable to 2.5 Gbit/s optical fiber communication systems.
