该文以单电感双输出(SIDO)Boost变换器为研究对象,详细分析电感电流工作于连续导电模式(CCM)的共模-差模电压型(CMV-DMV)控制SIDO Boost变换器的工作原理。采用时间平均等效电路建模方法,推导主电路的控制-输出、输出阻抗、交叉影响阻...该文以单电感双输出(SIDO)Boost变换器为研究对象,详细分析电感电流工作于连续导电模式(CCM)的共模-差模电压型(CMV-DMV)控制SIDO Boost变换器的工作原理。采用时间平均等效电路建模方法,推导主电路的控制-输出、输出阻抗、交叉影响阻抗等传递函数。在此基础上,建立CMV-DMV控制CCM SIDO Boost变换器的闭环小信号模型,并利用Bode图从频域的角度分析变换器两条输出支路在不同输出电压等级下的交叉影响特性。研究结果表明,在两路输出电压不等时,CMV-DMV控制CCM SIDO Boost变换器的高压输出支路对低压输出支路的交叉影响较小;在两路输出电压相等时,先导通输出支路对后导通输出支路的交叉影响较大。实验结果验证了理论分析的正确性。展开更多
Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementat...Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.展开更多
文摘该文以单电感双输出(SIDO)Boost变换器为研究对象,详细分析电感电流工作于连续导电模式(CCM)的共模-差模电压型(CMV-DMV)控制SIDO Boost变换器的工作原理。采用时间平均等效电路建模方法,推导主电路的控制-输出、输出阻抗、交叉影响阻抗等传递函数。在此基础上,建立CMV-DMV控制CCM SIDO Boost变换器的闭环小信号模型,并利用Bode图从频域的角度分析变换器两条输出支路在不同输出电压等级下的交叉影响特性。研究结果表明,在两路输出电压不等时,CMV-DMV控制CCM SIDO Boost变换器的高压输出支路对低压输出支路的交叉影响较小;在两路输出电压相等时,先导通输出支路对后导通输出支路的交叉影响较大。实验结果验证了理论分析的正确性。
文摘Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.
