A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity re...A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.展开更多
A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a hig...A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.展开更多
A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch "on" resistance. With the gain-boost technology,the operation...A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch "on" resistance. With the gain-boost technology,the operational transconductance amplifier used in this analog-to-digital converter (ADC) achieves enough DC gain and unity-gain frequency under the low voltage supply and to guarantee the performance of the sample and hold circuit (S/H) and the sub-stages. Based on these methods,a 10bit 100Msps pipelined ADC is fabricated in a 0. 18μm CMOS process and operates under a 1.8V voltage supply. The ADC achieves an SNR of 54. 2dB (input frequency of 6.26MHz) and an SNR of 49. 8dB (input frequency of 48. 96MHz) when the sampling frequency is 100MHz.展开更多
A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits i...A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.展开更多
This paper presents a novel mega-Hz-level super high frequency zero-voltage soft-switching converter for induction heating power supplies. The prominent advantage of this topology is that it can absorb both inductive ...This paper presents a novel mega-Hz-level super high frequency zero-voltage soft-switching converter for induction heating power supplies. The prominent advantage of this topology is that it can absorb both inductive and capacitive parasitic components in the converter. The switch devices operate in a zero-voltage soft-switching mode. Consequently, the high voltage and high current spikes caused by parasitic inductors or capacitors oscillation do not occur in this circuit, and the high power loss caused by high frequency switching can be greatly reduced. A large value inductor is adopted between the input capacitor and the switches, thus, this novel converter shares the benefits of both voltage-type and current-type circuits simultaneously, and there are no needs of dead time between two switches. The working principles in different modes are introduced. Results of simulation and experiments operated at around 1 MHz frequency verify the validity of parasitic components absorption and show that this convener is competent for super high frequency applications.展开更多
A new family of converters,high-performance AC/DC power factor correction(PFC) switching converters with one-cycle control technology and active floating-charge technology,was derived and experimentally verified.The t...A new family of converters,high-performance AC/DC power factor correction(PFC) switching converters with one-cycle control technology and active floating-charge technology,was derived and experimentally verified.The topology of a single-phase CCM and DCM Boost-PFC switching converter was also analyzed.Its operating prniciples and control methods were expounded.Based on these,a new type of AC/DC switching converter circuits for PFC combined with one-cycle control technology was presented herein.The proposed AC/DC switching converter significantly helps improve the converter efficiency and its power factor value.展开更多
The hysteresis control combined with PWM control non-inverting buck-boost was proposed to improve the light load efficiency and power density.The constant inductor current control(CICC)was established to mitigate the ...The hysteresis control combined with PWM control non-inverting buck-boost was proposed to improve the light load efficiency and power density.The constant inductor current control(CICC)was established to mitigate the dependence on the external components and device variation and make smooth transition between hysteresis control loop and pulse width modulation(PWM)control loop.The small signal model was deduced for the buck and boost operation mode.The inductor current slope control(ICSC)was proposed to implement the automatic mode transition between buck and boost mode in one switching cycle.The results show that the converter prototype has good dynamic response capability,achieving 94%efficiency and 95%peak efficiency at full 10 A load current.展开更多
A rearrangeable nonblocking silicon-on-insulator-based thermo-optic 4x4 switch matrix with spot size converters (SSCs) and a new driving circuit are designed and fabricated. The introduction of a spot size converter...A rearrangeable nonblocking silicon-on-insulator-based thermo-optic 4x4 switch matrix with spot size converters (SSCs) and a new driving circuit are designed and fabricated. The introduction of a spot size converter (SSC) has decreased the insertion loss to less than 10dB and the new driving circuit has improved the response speed to less than l^s.展开更多
With the development of devices for high performance, the circuit technologies have been also studied. One of the main streams concerns a soft switching technology to mitigate switching stress, leading to the reductio...With the development of devices for high performance, the circuit technologies have been also studied. One of the main streams concerns a soft switching technology to mitigate switching stress, leading to the reduction in switching losses or electro-magnetic noise. On the other hand, as a characterized orthodox technology', the existing chopper circuit is used for the electric vehicles, etc.. Such technologies have a tendency to go out of vogue as power supplies for such vehicles. However, as a boost chopper for the battery charger for an electric vehicle, those technologies become a main stream, where a bilateral function is required. With the foregoing in mind, the authors have devised and analyzed the bilateral chopper using the soft-switch technology, which could be applied to a battery charger for an electric vehicle or similar.展开更多
A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase...A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.展开更多
This paper presents a new approach to alleviate the harmonics and to enhance the power factor of the ASD (adjustable speed drive). A conventional ASD with 2-level PWM (pulse width modulation) inverters generate hi...This paper presents a new approach to alleviate the harmonics and to enhance the power factor of the ASD (adjustable speed drive). A conventional ASD with 2-level PWM (pulse width modulation) inverters generate high dv/dt and high frequency common mode voltages which are harmful for the drive applications. It reduces the motor bearings life and conducted EMI (electro magnetic interference) deteriorates the insulation. In this paper, a diode clamped multilevel (3-level) inverter is used to perform dual task. It generates HF (high frequency) current to be injected at the input of the three-phase front-end rectifier thereby improving the harmonic spectra and the power factor. It also drives the induction motor. The salient feature of this paper is that it does not require separate converters for improving power factor and to drive induction motor. Furthermore, inverter switches operate with ZVS (zero voltage switching), thus reducing the switching losses substantially, The voltage stress of the switches also has been reduced to half of the conventional 2-level converter. The inverter is operated with SPWM (sinusoidal pulse width modulation) technique. The simulation results for a prototype of 2.2 kW are presented.展开更多
The multi-phase implementation in the QR (quasi resonant) ZCS (zero current switching) SC (switched capacitor) bidirectional DC-DC converter structure has been proposed to reduce current ripple, switching loss a...The multi-phase implementation in the QR (quasi resonant) ZCS (zero current switching) SC (switched capacitor) bidirectional DC-DC converter structure has been proposed to reduce current ripple, switching loss and significantly increase the converter efficiency and power density. This approach provides a more precise output voltage to obtain voltage conversion ratios from the double-mode versus half-mode to n-mode versus 1/n mode. This is accomplished by adding a different number of switched-capacitors and power MOSFET switches with a small series connected resonant inductor for forward and reverse schemes. The size and cost can be reduced when the proposed converter has been designed with the coupled inductors. The simulation and experimental results have been used to demonstrate the performance of the two-phase with and without coupled inductor interleaved QR ZCS SC converters for bidirectional power flow control application, and an extending structure for N-phase is mentioned.展开更多
The adapted DC-DC converters should be smaller in size and have a small output current ripple to meet the increasing demand for low voltages with high performance and high density micro processors for several microele...The adapted DC-DC converters should be smaller in size and have a small output current ripple to meet the increasing demand for low voltages with high performance and high density micro processors for several microelectronic load applications. This paper proposes a DC-DC converter using variable on-time and variable switching frequency control enhanced constant ripple current control and reduced magnetic components. The proposed converter is realized by making the turn-offtime proportional to the on-time of the converter, according to the input and output voltage, thereby reducing the corresponding current ripple on output voltage in the continuous conduction mode. A Buck DC-DC converter using the proposed control strategy is analyzed in detail, along with some experimental results to show the performance and effectiveness of this converter.展开更多
This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in ...This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.展开更多
Partial shading and mismatch conditions among the series-connected modules/sub-modules suffer from a nonconvex power curve with multiple local maxima and decreased peak power for the whole string. Energy transfer betw...Partial shading and mismatch conditions among the series-connected modules/sub-modules suffer from a nonconvex power curve with multiple local maxima and decreased peak power for the whole string. Energy transfer between the sub-modules brings them to the same operating voltage, and this collective operation produces a convex power curve, which results in increased peak power for the string. The proposed topology benefits from the switched-capacitor (SC) converter concept and is an application for sub-module-level power balancing with some novelties, including stopping the switching in absence of shading, string-level extension, and a reduced number of power electronics components as compared to those in the literature. Reduction in the number of power electronics components is realized by the fact that two sub-modules share one SC converter. This leads to reduced power electronics losses as well as less cost and volume of the converter circuit. Insertion loss analysis of the topology is presented. The proposed topology is simulated in the PSpice environment, and a prototype is built for experimental verification. Both simulation and experimental results confirm the loss analysis. This proves that with the proposed topology it is possible to extract almost all the power available on the partially shaded string and transfer it to the load side.展开更多
During the past decades,nonlinear optical(NLO)materials have attracted special interest because of their potential applications in photonic devices,such as optical switching,frequency conversion and electro-optic mo...During the past decades,nonlinear optical(NLO)materials have attracted special interest because of their potential applications in photonic devices,such as optical switching,frequency conversion and electro-optic modulators.Among the finding ways to obtain excellent NLO materials with both large NLO response and short response time,展开更多
文摘A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.
文摘A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.
文摘A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch "on" resistance. With the gain-boost technology,the operational transconductance amplifier used in this analog-to-digital converter (ADC) achieves enough DC gain and unity-gain frequency under the low voltage supply and to guarantee the performance of the sample and hold circuit (S/H) and the sub-stages. Based on these methods,a 10bit 100Msps pipelined ADC is fabricated in a 0. 18μm CMOS process and operates under a 1.8V voltage supply. The ADC achieves an SNR of 54. 2dB (input frequency of 6.26MHz) and an SNR of 49. 8dB (input frequency of 48. 96MHz) when the sampling frequency is 100MHz.
文摘A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.
文摘This paper presents a novel mega-Hz-level super high frequency zero-voltage soft-switching converter for induction heating power supplies. The prominent advantage of this topology is that it can absorb both inductive and capacitive parasitic components in the converter. The switch devices operate in a zero-voltage soft-switching mode. Consequently, the high voltage and high current spikes caused by parasitic inductors or capacitors oscillation do not occur in this circuit, and the high power loss caused by high frequency switching can be greatly reduced. A large value inductor is adopted between the input capacitor and the switches, thus, this novel converter shares the benefits of both voltage-type and current-type circuits simultaneously, and there are no needs of dead time between two switches. The working principles in different modes are introduced. Results of simulation and experiments operated at around 1 MHz frequency verify the validity of parasitic components absorption and show that this convener is competent for super high frequency applications.
文摘A new family of converters,high-performance AC/DC power factor correction(PFC) switching converters with one-cycle control technology and active floating-charge technology,was derived and experimentally verified.The topology of a single-phase CCM and DCM Boost-PFC switching converter was also analyzed.Its operating prniciples and control methods were expounded.Based on these,a new type of AC/DC switching converter circuits for PFC combined with one-cycle control technology was presented herein.The proposed AC/DC switching converter significantly helps improve the converter efficiency and its power factor value.
文摘The hysteresis control combined with PWM control non-inverting buck-boost was proposed to improve the light load efficiency and power density.The constant inductor current control(CICC)was established to mitigate the dependence on the external components and device variation and make smooth transition between hysteresis control loop and pulse width modulation(PWM)control loop.The small signal model was deduced for the buck and boost operation mode.The inductor current slope control(ICSC)was proposed to implement the automatic mode transition between buck and boost mode in one switching cycle.The results show that the converter prototype has good dynamic response capability,achieving 94%efficiency and 95%peak efficiency at full 10 A load current.
基金Supported in part by the National Key Basic Research Special Foundation of China under Grant No. G2000-03-66the Na-tional High Technology Program of China under Grant No.2002AA312060the National Natural Science Foundation ofChina under Grant No. 60336010.
文摘A rearrangeable nonblocking silicon-on-insulator-based thermo-optic 4x4 switch matrix with spot size converters (SSCs) and a new driving circuit are designed and fabricated. The introduction of a spot size converter (SSC) has decreased the insertion loss to less than 10dB and the new driving circuit has improved the response speed to less than l^s.
文摘With the development of devices for high performance, the circuit technologies have been also studied. One of the main streams concerns a soft switching technology to mitigate switching stress, leading to the reduction in switching losses or electro-magnetic noise. On the other hand, as a characterized orthodox technology', the existing chopper circuit is used for the electric vehicles, etc.. Such technologies have a tendency to go out of vogue as power supplies for such vehicles. However, as a boost chopper for the battery charger for an electric vehicle, those technologies become a main stream, where a bilateral function is required. With the foregoing in mind, the authors have devised and analyzed the bilateral chopper using the soft-switch technology, which could be applied to a battery charger for an electric vehicle or similar.
基金Supported by National Natural Science Foundation of China (No.60806010,No.60976030)
文摘A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.
文摘This paper presents a new approach to alleviate the harmonics and to enhance the power factor of the ASD (adjustable speed drive). A conventional ASD with 2-level PWM (pulse width modulation) inverters generate high dv/dt and high frequency common mode voltages which are harmful for the drive applications. It reduces the motor bearings life and conducted EMI (electro magnetic interference) deteriorates the insulation. In this paper, a diode clamped multilevel (3-level) inverter is used to perform dual task. It generates HF (high frequency) current to be injected at the input of the three-phase front-end rectifier thereby improving the harmonic spectra and the power factor. It also drives the induction motor. The salient feature of this paper is that it does not require separate converters for improving power factor and to drive induction motor. Furthermore, inverter switches operate with ZVS (zero voltage switching), thus reducing the switching losses substantially, The voltage stress of the switches also has been reduced to half of the conventional 2-level converter. The inverter is operated with SPWM (sinusoidal pulse width modulation) technique. The simulation results for a prototype of 2.2 kW are presented.
文摘The multi-phase implementation in the QR (quasi resonant) ZCS (zero current switching) SC (switched capacitor) bidirectional DC-DC converter structure has been proposed to reduce current ripple, switching loss and significantly increase the converter efficiency and power density. This approach provides a more precise output voltage to obtain voltage conversion ratios from the double-mode versus half-mode to n-mode versus 1/n mode. This is accomplished by adding a different number of switched-capacitors and power MOSFET switches with a small series connected resonant inductor for forward and reverse schemes. The size and cost can be reduced when the proposed converter has been designed with the coupled inductors. The simulation and experimental results have been used to demonstrate the performance of the two-phase with and without coupled inductor interleaved QR ZCS SC converters for bidirectional power flow control application, and an extending structure for N-phase is mentioned.
文摘The adapted DC-DC converters should be smaller in size and have a small output current ripple to meet the increasing demand for low voltages with high performance and high density micro processors for several microelectronic load applications. This paper proposes a DC-DC converter using variable on-time and variable switching frequency control enhanced constant ripple current control and reduced magnetic components. The proposed converter is realized by making the turn-offtime proportional to the on-time of the converter, according to the input and output voltage, thereby reducing the corresponding current ripple on output voltage in the continuous conduction mode. A Buck DC-DC converter using the proposed control strategy is analyzed in detail, along with some experimental results to show the performance and effectiveness of this converter.
文摘This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.
基金Project supported by the BAP Department of Karabuk University,Turkey(No.KBU-BAP-13/2-DR-010)
文摘Partial shading and mismatch conditions among the series-connected modules/sub-modules suffer from a nonconvex power curve with multiple local maxima and decreased peak power for the whole string. Energy transfer between the sub-modules brings them to the same operating voltage, and this collective operation produces a convex power curve, which results in increased peak power for the string. The proposed topology benefits from the switched-capacitor (SC) converter concept and is an application for sub-module-level power balancing with some novelties, including stopping the switching in absence of shading, string-level extension, and a reduced number of power electronics components as compared to those in the literature. Reduction in the number of power electronics components is realized by the fact that two sub-modules share one SC converter. This leads to reduced power electronics losses as well as less cost and volume of the converter circuit. Insertion loss analysis of the topology is presented. The proposed topology is simulated in the PSpice environment, and a prototype is built for experimental verification. Both simulation and experimental results confirm the loss analysis. This proves that with the proposed topology it is possible to extract almost all the power available on the partially shaded string and transfer it to the load side.
基金supported by the National Natural Science Foundation of China(Grant No.11474046)Program for New Century Excellent Talents in University(Grant No.NCET-13-0702)+3 种基金Fundamental Research Funds for the Central Universities(Grant Nos.DC201502080202,and DC201502080203)Program for Liaoning Excellent Talents in University(LNET)(Grant No.LR2015016)Science and Technique Foundation of Dalian(Grant Nos.2014J11JH134,and 2015J12JH201)Education Department of Liaoning Province of China.
文摘During the past decades,nonlinear optical(NLO)materials have attracted special interest because of their potential applications in photonic devices,such as optical switching,frequency conversion and electro-optic modulators.Among the finding ways to obtain excellent NLO materials with both large NLO response and short response time,