In order to improve the use efficiency of curb parking, a reasonable curb parking pricing is evaluated by considering individual parking choice behavior. The parking choice behavior is analyzed from micro-aspects, and...In order to improve the use efficiency of curb parking, a reasonable curb parking pricing is evaluated by considering individual parking choice behavior. The parking choice behavior is analyzed from micro-aspects, and the choice behavior utility function is established combining trip time, search time, waiting time, access time and parking fee. By the utility function, a probit-based parking choice behavior model is constructed. On the basis of these, the curb parking pricing model is deduced by considering the constrained conditions, and an incremental assignment algorithm of the model is also designed. Finally, the model is applied to the parking planning of Tongling city. It is pointed out that the average parking time of curb parking decreases 34%, and the average turnover rate increases 67% under the computed parking price system. The results show that the model can optimize the utilization of static traffic facilities.展开更多
A simple graph G on n vettices is said to be a simple MCD-graph if G has no two cyties having the same length and has the maximum possible number of edges.Two results of the number of cy cles in G are given by introdu...A simple graph G on n vettices is said to be a simple MCD-graph if G has no two cyties having the same length and has the maximum possible number of edges.Two results of the number of cy cles in G are given by introdueing the Concept of a path decomposition and by them,the following theorem is proved:If G is a simple MCD-graph,then G is not a 2-connected planar graph and for all n except seven integer,G is not a 2-connected graph on n vertices containing a subgraph homeomor phic to K_4.展开更多
A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented witho...A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.展开更多
Accessing the bypassed portion of the stomach via conventional endoscopy is difficult following Roux-en-Y gastric bypass surgery. However, endoscopic examination of the stomach and small bowel is possible through perc...Accessing the bypassed portion of the stomach via conventional endoscopy is difficult following Roux-en-Y gastric bypass surgery. However, endoscopic examination of the stomach and small bowel is possible through percutaneous access into the bypassed stomach (BS) with a combined radiologic and endoscopic technique. We present a case of obscure overt gastrointestinal (GI) bleeding where the source of bleeding was thought to be from the BS. After conventional endoscopic methods failed to examine the BS, percutaneous endoscopy (PE) was used as an alternative to surgical exploration.展开更多
An adaptive ramp generator based on linear histogram was proposed for the built-in selftest (BIST) of analog to digital convertor (ADC) in CMOS image sensor. By comparing the generated ramp signal to a reference volta...An adaptive ramp generator based on linear histogram was proposed for the built-in selftest (BIST) of analog to digital convertor (ADC) in CMOS image sensor. By comparing the generated ramp signal to a reference voltage and feeding back a calibration signal, the slope adjustment was implemented, and high linearity and precision of ramp slope were realized. By modulating the pulse width and reference voltage, sweep length varied from microsecond to second and signal swing could reach 3 V with 5.6 mW power consumption. The ramp was used as input to an ideal 10-bit single-slope ADC, and the corresponding DNL and INL were 0.032 LSB and 0.078 LSB, re-spectively.展开更多
This paper presents an analog circuit built-in-test （BIT） structure based on boundary scan and realizes the BI＇I. It predigests the test process and improves the test precision by taking the rectangular pulse as st...This paper presents an analog circuit built-in-test （BIT） structure based on boundary scan and realizes the BI＇I. It predigests the test process and improves the test precision by taking the rectangular pulse as stimulator and analog switch as auxiliary bridge. The experiment of uA741 shows that the design is feasible. Compared with the traditional test method, it is better regarding reliability and measurability of the analog circuit system.展开更多
基金The National Natural Science Foundation of China(No50308005), the National Basic Research Program of China (973Program) (No2006CB705500)
文摘In order to improve the use efficiency of curb parking, a reasonable curb parking pricing is evaluated by considering individual parking choice behavior. The parking choice behavior is analyzed from micro-aspects, and the choice behavior utility function is established combining trip time, search time, waiting time, access time and parking fee. By the utility function, a probit-based parking choice behavior model is constructed. On the basis of these, the curb parking pricing model is deduced by considering the constrained conditions, and an incremental assignment algorithm of the model is also designed. Finally, the model is applied to the parking planning of Tongling city. It is pointed out that the average parking time of curb parking decreases 34%, and the average turnover rate increases 67% under the computed parking price system. The results show that the model can optimize the utilization of static traffic facilities.
文摘A simple graph G on n vettices is said to be a simple MCD-graph if G has no two cyties having the same length and has the maximum possible number of edges.Two results of the number of cy cles in G are given by introdueing the Concept of a path decomposition and by them,the following theorem is proved:If G is a simple MCD-graph,then G is not a 2-connected planar graph and for all n except seven integer,G is not a 2-connected graph on n vertices containing a subgraph homeomor phic to K_4.
文摘A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.
文摘Accessing the bypassed portion of the stomach via conventional endoscopy is difficult following Roux-en-Y gastric bypass surgery. However, endoscopic examination of the stomach and small bowel is possible through percutaneous access into the bypassed stomach (BS) with a combined radiologic and endoscopic technique. We present a case of obscure overt gastrointestinal (GI) bleeding where the source of bleeding was thought to be from the BS. After conventional endoscopic methods failed to examine the BS, percutaneous endoscopy (PE) was used as an alternative to surgical exploration.
基金National Natural Science Foundation of China(No.60576025)Tianjin Science and Technology Development Program (No.06YFGZGX03400)
文摘An adaptive ramp generator based on linear histogram was proposed for the built-in selftest (BIST) of analog to digital convertor (ADC) in CMOS image sensor. By comparing the generated ramp signal to a reference voltage and feeding back a calibration signal, the slope adjustment was implemented, and high linearity and precision of ramp slope were realized. By modulating the pulse width and reference voltage, sweep length varied from microsecond to second and signal swing could reach 3 V with 5.6 mW power consumption. The ramp was used as input to an ideal 10-bit single-slope ADC, and the corresponding DNL and INL were 0.032 LSB and 0.078 LSB, re-spectively.
文摘This paper presents an analog circuit built-in-test （BIT） structure based on boundary scan and realizes the BI＇I. It predigests the test process and improves the test precision by taking the rectangular pulse as stimulator and analog switch as auxiliary bridge. The experiment of uA741 shows that the design is feasible. Compared with the traditional test method, it is better regarding reliability and measurability of the analog circuit system.
