This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order t...This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order to reduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM is constructed. The optimized LPSR SRAM64K × 32 is used in SoC and the testing method of the LPSR SRAM64K × 32 is also discussed. The SoC design is successfully implemented in the Chartered 90nm CMOS process. The SoC chip occupies 5. 6mm× 5. 6ram of die area and the power dissipation is 1997mW. The test results indicate that LPSR SRAM64K ×32 obtains 17. 301% power savings and the yield of the LPSR SRAM64K × 32s per wafer is improved by 13. 255%.展开更多
The enhanced variable rate codec (EVRC) is a standard for the 'Speech ServiceOption 3 for Wideband Spread Spectrum Digital System,' which has been employed in both IS-95cellular systems and ANSI J-STC-008 PCS ...The enhanced variable rate codec (EVRC) is a standard for the 'Speech ServiceOption 3 for Wideband Spread Spectrum Digital System,' which has been employed in both IS-95cellular systems and ANSI J-STC-008 PCS (personal communications systems). This paper concentrateson channel decoders that exploit the residual redundancy inherent in the enhanced variable ratecodec bitstream. This residual redundancy is quantified by modeling the parameters as first orderMarkov chains and computing the entropy rate based on the relative frequencies of transitions.Moreover, this residual redundancy can be exploited by an appropriately 'tuned' channel decoder toprovide substantial coding gain when compared with the decoders that do not exploit it. Channelcoding schemes include convolutional codes, and iteratively decoded parallel concatenatedconvolutional 'turbo' codes.展开更多
文摘This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order to reduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM is constructed. The optimized LPSR SRAM64K × 32 is used in SoC and the testing method of the LPSR SRAM64K × 32 is also discussed. The SoC design is successfully implemented in the Chartered 90nm CMOS process. The SoC chip occupies 5. 6mm× 5. 6ram of die area and the power dissipation is 1997mW. The test results indicate that LPSR SRAM64K ×32 obtains 17. 301% power savings and the yield of the LPSR SRAM64K × 32s per wafer is improved by 13. 255%.
文摘The enhanced variable rate codec (EVRC) is a standard for the 'Speech ServiceOption 3 for Wideband Spread Spectrum Digital System,' which has been employed in both IS-95cellular systems and ANSI J-STC-008 PCS (personal communications systems). This paper concentrateson channel decoders that exploit the residual redundancy inherent in the enhanced variable ratecodec bitstream. This residual redundancy is quantified by modeling the parameters as first orderMarkov chains and computing the entropy rate based on the relative frequencies of transitions.Moreover, this residual redundancy can be exploited by an appropriately 'tuned' channel decoder toprovide substantial coding gain when compared with the decoders that do not exploit it. Channelcoding schemes include convolutional codes, and iteratively decoded parallel concatenatedconvolutional 'turbo' codes.
