Slack-Decode Simultaneously and Redundantly Threaded （SD-SRT） is proposed for detecting transient faults in processors. SD-SRT boosts the previously proposed SRT performance via definitely eliminating redundant inst...Slack-Decode Simultaneously and Redundantly Threaded （SD-SRT） is proposed for detecting transient faults in processors. SD-SRT boosts the previously proposed SRT performance via definitely eliminating redundant instructiou fetches. First, the fetch stage is moved out of the Spheres of Replication （SoR）, and a unified instruction-fetch-queue （IFQ） is exploited by both the leading and trailing threads. Second, a scheme called slack-decode cooperates with the unified IFQ to harmonize proceeding of the two threads. The simulations show that SD-SRT outperforms original SRT in terms of IPC by 15%, and decreases I-cache access by 42%. Meanwhile, SD-SRT leads to a lessened size and complexity for hardware structures such as load-value-queue and store-buffer.展开更多
The problems of current highly redundant flight control system are analyzed in this paper. Our study gives methods of utilizing other information to reduce physical components on the condition of meeting the reliabili...The problems of current highly redundant flight control system are analyzed in this paper. Our study gives methods of utilizing other information to reduce physical components on the condition of meeting the reliability requirements for flight control system. The strategies presented in this paper mainly include information redundancy, multi-thread, time redundancy, geometry space redundancy, etc.. Analysis and simulation show these non-hardware based methods can reduce the requirement of system hardware level and thus reduce the system complexity, weight, space, costs and R＆D （research and development） time.展开更多
The State Transition Equation (STE) based method to automatically generate the parallel CRC circuits for any generator polynomial or required amount of parallelism is presented. The parallel CRC circuit so generate...The State Transition Equation (STE) based method to automatically generate the parallel CRC circuits for any generator polynomial or required amount of parallelism is presented. The parallel CRC circuit so generated is partially optimized before being fed to synthesis tools and works properly in our LAN transceiv-er. Compared with the cascading method, the proposed method gives better timing results and significantly re-duces the synthesis time, in particular.展开更多
文摘Slack-Decode Simultaneously and Redundantly Threaded （SD-SRT） is proposed for detecting transient faults in processors. SD-SRT boosts the previously proposed SRT performance via definitely eliminating redundant instructiou fetches. First, the fetch stage is moved out of the Spheres of Replication （SoR）, and a unified instruction-fetch-queue （IFQ） is exploited by both the leading and trailing threads. Second, a scheme called slack-decode cooperates with the unified IFQ to harmonize proceeding of the two threads. The simulations show that SD-SRT outperforms original SRT in terms of IPC by 15%, and decreases I-cache access by 42%. Meanwhile, SD-SRT leads to a lessened size and complexity for hardware structures such as load-value-queue and store-buffer.
文摘The problems of current highly redundant flight control system are analyzed in this paper. Our study gives methods of utilizing other information to reduce physical components on the condition of meeting the reliability requirements for flight control system. The strategies presented in this paper mainly include information redundancy, multi-thread, time redundancy, geometry space redundancy, etc.. Analysis and simulation show these non-hardware based methods can reduce the requirement of system hardware level and thus reduce the system complexity, weight, space, costs and R＆D （research and development） time.
文摘The State Transition Equation (STE) based method to automatically generate the parallel CRC circuits for any generator polynomial or required amount of parallelism is presented. The parallel CRC circuit so generated is partially optimized before being fed to synthesis tools and works properly in our LAN transceiv-er. Compared with the cascading method, the proposed method gives better timing results and significantly re-duces the synthesis time, in particular.
