A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is...A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.展开更多
The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communi...The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.展开更多
An accurate technique for measuring the frequency response of semiconductor laser diode chips is proposed and experimentally demonstrated.The effects of test jig parasites can be completely removed in the measurement ...An accurate technique for measuring the frequency response of semiconductor laser diode chips is proposed and experimentally demonstrated.The effects of test jig parasites can be completely removed in the measurement by a new calibration method.In theory,the measuring range of the measurement system is only determined by the measuring range of the instruments network analyzer and photo detector.Diodes' bandwidth of 7 5GHz and 10GHz is measured.The results reveal that the method is feasible and comparing with other method,it is more precise and easier to use.展开更多
A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant ac...A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.展开更多
Fluidization characteristics of silicon particle system are studied by the pressure fluctuation method.The existence of fine particles in the system can improve fluidization. Silicon particles with a wide size distrib...Fluidization characteristics of silicon particle system are studied by the pressure fluctuation method.The existence of fine particles in the system can improve fluidization. Silicon particles with a wide size distribution,preferably with some fines, behave as Group A particles according to Geldart classification, although the system belongs to Group B actually. The system is also approved to be suitable for organochlorosilane monomer production using a fluidized bed reactor. Experimental data obtained in this work are important for the design and operation of commercial fluidized bed reactors for the production of organochlorosilane monomers.展开更多
The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main ...The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.展开更多
This letter proposes a rate control algorithm for H.264 video encoder, which is based on block activity and buffer state. Experimental results indicate that it has an excellent performance by providing much accurate b...This letter proposes a rate control algorithm for H.264 video encoder, which is based on block activity and buffer state. Experimental results indicate that it has an excellent performance by providing much accurate bit rate and better coding efficiency compared with H.264. The computational complexity of the algorithm is reduced by adopting a novel block activity description method using the Sum of Absolute Difference (SAD) of 16× 16 mode, and its robustness is enhanced by introducing a feedback circuit at frame layer.展开更多
This study was conducted to explore the individual uses of formulaic sequence(FS)frequency and their effects on complexity,accuracy,and fluency(CAF)in academic writing.Data was collected from the conclusion sections o...This study was conducted to explore the individual uses of formulaic sequence(FS)frequency and their effects on complexity,accuracy,and fluency(CAF)in academic writing.Data was collected from the conclusion sections of a self-compiled corpus of 30 L2 master’s theses.Statistical analysis revealed several notable conclusions.1)Student writers tend to make repetitive use of particular FSs in single texts.2)FS use has a significant frequency effect on fluency,and the high-frequency group slightly outperforms the low-frequency group.3)FS use has a certain frequency effect on accuracy,and the high-frequency group demonstrates the strongest correlation between FS frequency and accuracy.4)FS use has a significant frequency effect on lexical complexity,and the low-frequency group slightly outperforms the high-frequency group.In the low-frequency group,FS use has a significant frequency effect on syntactic complexity as well.Finally,5)The results support Skehan’s trade-off effect,a competition between CAF,which,to a certain degree,is affected by individual uses of FS frequency.The low-frequency group displays a greater trade-off effect than the high-frequency group.展开更多
Radio Frequency Interference (RFI) degrades the quality of focused Ultra-WideBand Syn- thetic Aperture Radar (UWB SAR) images. From both the theoretical analysis and real data valida- tion, it is concluded that target...Radio Frequency Interference (RFI) degrades the quality of focused Ultra-WideBand Syn- thetic Aperture Radar (UWB SAR) images. From both the theoretical analysis and real data valida- tion, it is concluded that target echo and RFI have different Region Of Support (ROS) in 2-D fast- time wavenumber and aperture wavenumber domain. Consequently, a novel adaptive filter is pro- posed according to the Wiener optimum criterion on the distinct ROS characteristics of target echo and RFI. Compared with the notch filter and the Least Mean Square (LMS) adaptive filter in previ- ous literatures, the proposed method is more computationally efficient with satisfactory suppression results. In terms of Signal-to-Interference Ratio Improvement (SIRI) and processing time, the per- formance of the proposed adaptive filter is verified with the field data collected with a UWB SAR system.展开更多
文摘A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.
基金The National Natural Science Foundation of China(No.60472057)
文摘The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.
文摘An accurate technique for measuring the frequency response of semiconductor laser diode chips is proposed and experimentally demonstrated.The effects of test jig parasites can be completely removed in the measurement by a new calibration method.In theory,the measuring range of the measurement system is only determined by the measuring range of the instruments network analyzer and photo detector.Diodes' bandwidth of 7 5GHz and 10GHz is measured.The results reveal that the method is feasible and comparing with other method,it is more precise and easier to use.
基金The National High Technology Research and Development Program of China (863 Program)(No.2007AA01Z2A7)the Scienceand Technology Program of Zhejiang Province (No.2008C16017)
文摘A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.
文摘Fluidization characteristics of silicon particle system are studied by the pressure fluctuation method.The existence of fine particles in the system can improve fluidization. Silicon particles with a wide size distribution,preferably with some fines, behave as Group A particles according to Geldart classification, although the system belongs to Group B actually. The system is also approved to be suitable for organochlorosilane monomer production using a fluidized bed reactor. Experimental data obtained in this work are important for the design and operation of commercial fluidized bed reactors for the production of organochlorosilane monomers.
基金The National Natural Science Foundation of China(No60472057)
文摘The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.
基金the National Nature Science Foundation of China(No.90104013) 863 Project(No.2002AA119010, 2001AA121061 and 2002AA123041)
文摘This letter proposes a rate control algorithm for H.264 video encoder, which is based on block activity and buffer state. Experimental results indicate that it has an excellent performance by providing much accurate bit rate and better coding efficiency compared with H.264. The computational complexity of the algorithm is reduced by adopting a novel block activity description method using the Sum of Absolute Difference (SAD) of 16× 16 mode, and its robustness is enhanced by introducing a feedback circuit at frame layer.
基金This project was supported by China National Social Science Funding(No.18BYY107).
文摘This study was conducted to explore the individual uses of formulaic sequence(FS)frequency and their effects on complexity,accuracy,and fluency(CAF)in academic writing.Data was collected from the conclusion sections of a self-compiled corpus of 30 L2 master’s theses.Statistical analysis revealed several notable conclusions.1)Student writers tend to make repetitive use of particular FSs in single texts.2)FS use has a significant frequency effect on fluency,and the high-frequency group slightly outperforms the low-frequency group.3)FS use has a certain frequency effect on accuracy,and the high-frequency group demonstrates the strongest correlation between FS frequency and accuracy.4)FS use has a significant frequency effect on lexical complexity,and the low-frequency group slightly outperforms the high-frequency group.In the low-frequency group,FS use has a significant frequency effect on syntactic complexity as well.Finally,5)The results support Skehan’s trade-off effect,a competition between CAF,which,to a certain degree,is affected by individual uses of FS frequency.The low-frequency group displays a greater trade-off effect than the high-frequency group.
文摘Radio Frequency Interference (RFI) degrades the quality of focused Ultra-WideBand Syn- thetic Aperture Radar (UWB SAR) images. From both the theoretical analysis and real data valida- tion, it is concluded that target echo and RFI have different Region Of Support (ROS) in 2-D fast- time wavenumber and aperture wavenumber domain. Consequently, a novel adaptive filter is pro- posed according to the Wiener optimum criterion on the distinct ROS characteristics of target echo and RFI. Compared with the notch filter and the Least Mean Square (LMS) adaptive filter in previ- ous literatures, the proposed method is more computationally efficient with satisfactory suppression results. In terms of Signal-to-Interference Ratio Improvement (SIRI) and processing time, the per- formance of the proposed adaptive filter is verified with the field data collected with a UWB SAR system.
