This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. ...This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to low power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation （EDA） tools from Synopsy~ to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-ou-chips （SOC）. The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test m ADVANTEST.展开更多
文摘This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to low power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation （EDA） tools from Synopsy~ to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-ou-chips （SOC）. The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test m ADVANTEST.
