设计并模拟分析了光纤通信用超高速单电源 Ga As判决再生电路 ,采用非掺 SI Ga As衬底直接离子注入、1μm耗尽型 Ga As MESFET、平面电路工艺研制出单片 Ga As判决再生电路。实验测试结果表明 ,该电路可对输入信号进行正确的“0”、“1...设计并模拟分析了光纤通信用超高速单电源 Ga As判决再生电路 ,采用非掺 SI Ga As衬底直接离子注入、1μm耗尽型 Ga As MESFET、平面电路工艺研制出单片 Ga As判决再生电路。实验测试结果表明 ,该电路可对输入信号进行正确的“0”、“1”判决 ,并经时钟抽样后 ,输出正确的数字信号 ,传输速率可达 2 .8Gbit/s,可用于覆盖 2 .展开更多
A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency div...A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.展开更多
A 2 5Gb/s depletion mode GaAs MESFET clock recovery and decision circuit is described,which applies to the optical fiber communication.The circuit consists of a clock recovery circuit,including a preprocessor,phase ...A 2 5Gb/s depletion mode GaAs MESFET clock recovery and decision circuit is described,which applies to the optical fiber communication.The circuit consists of a clock recovery circuit,including a preprocessor,phase detector(PD),low pass filter(LPF) and voltage controlled oscillator(VCO) and a decision circuit,including a comparator and a latch.The SPICE simulation result confirms the high frequency 2 5GHz of the clock recovery and the high speed 2 5Gb/s of the decision circuit.The 2 5Gb/s decision circuit has proved to be able to deal with the input signal and produce a digital output signal after it being sampled by a clock signal.展开更多
This paper presents a method based on a sample-decision(SD) circuit to suppress crosstalk and noise for a high-speed and high-density bus system.A method to count the number of times of SD for different length of tran...This paper presents a method based on a sample-decision(SD) circuit to suppress crosstalk and noise for a high-speed and high-density bus system.A method to count the number of times of SD for different length of transmission lines is presented and a bit error rates(BERs) formula is given by the SD circuit.It is shown that for long transmission line systems,multiple SD circuits can improve the BERs significantly.Circuits simulation for single SD method is also done,it is found that when the amplitude peak values of the superposed crosstalk and noise are less than half of the corresponding signal ones,they will be eliminated completely for the cases investigated.展开更多
文摘设计并模拟分析了光纤通信用超高速单电源 Ga As判决再生电路 ,采用非掺 SI Ga As衬底直接离子注入、1μm耗尽型 Ga As MESFET、平面电路工艺研制出单片 Ga As判决再生电路。实验测试结果表明 ,该电路可对输入信号进行正确的“0”、“1”判决 ,并经时钟抽样后 ,输出正确的数字信号 ,传输速率可达 2 .8Gbit/s,可用于覆盖 2 .
文摘A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.
文摘A 2 5Gb/s depletion mode GaAs MESFET clock recovery and decision circuit is described,which applies to the optical fiber communication.The circuit consists of a clock recovery circuit,including a preprocessor,phase detector(PD),low pass filter(LPF) and voltage controlled oscillator(VCO) and a decision circuit,including a comparator and a latch.The SPICE simulation result confirms the high frequency 2 5GHz of the clock recovery and the high speed 2 5Gb/s of the decision circuit.The 2 5Gb/s decision circuit has proved to be able to deal with the input signal and produce a digital output signal after it being sampled by a clock signal.
基金Supported by the National Natural Science Foundation of China(No.61171039,61072059)
文摘This paper presents a method based on a sample-decision(SD) circuit to suppress crosstalk and noise for a high-speed and high-density bus system.A method to count the number of times of SD for different length of transmission lines is presented and a bit error rates(BERs) formula is given by the SD circuit.It is shown that for long transmission line systems,multiple SD circuits can improve the BERs significantly.Circuits simulation for single SD method is also done,it is found that when the amplitude peak values of the superposed crosstalk and noise are less than half of the corresponding signal ones,they will be eliminated completely for the cases investigated.
