A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short...A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.展开更多
A compact Ka-band monolithic microwave integrated circuit(MMIC) voltage controlled oscillator (VCO) with wide tuning range and high output power,which is based on GaAs PHEMT process,is presented.A method is introduced...A compact Ka-band monolithic microwave integrated circuit(MMIC) voltage controlled oscillator (VCO) with wide tuning range and high output power,which is based on GaAs PHEMT process,is presented.A method is introduced to reduce the chip size and to increase the bandwidth of operation.The procedure to design a MMIC VCO is also described here.The measured oscillating frequency of the MMIC VCO is 36±1.2GHz and the output power is 10±1dBm.The fabricated MMIC chip size is 1.3mm×1.0mm.展开更多
We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital c...We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital controller, the proposed DPWM can not only offer temperature/process-independent pulse widths, but also operate at a much higher clock frequency than the existing delay-line/counter DPWM structure. Post-simulation results show that with our DPWM, the system clock frequency reaches 156.9MHz while the worst variation,in a temperature range of 0 to 100℃under all process corners,is only± 9.4%.展开更多
In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for...In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.展开更多
A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range （from 1. 8998 to 2. 2335GHz） through a combination of analog and digital tun...A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range （from 1. 8998 to 2. 2335GHz） through a combination of analog and digital tuning techniques （4-bit binary switch-capacitor array）. The measured phase noise is - 118.17dBc/Hz at a 1MHz offset from a 2. 158GHz carrier. With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits. The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors. The VCO draws a current of about 2. lmA from a 1.8V power supply and works normally with a 1.5V power supply.展开更多
This paper lenges in the design of discusses some chal- millimeter-wave （mln- wave） circuits and systems for 5th generation （5G） wireless systems in CMOS process. The properties of some passive and active devices ...This paper lenges in the design of discusses some chal- millimeter-wave （mln- wave） circuits and systems for 5th generation （5G） wireless systems in CMOS process. The properties of some passive and active devices such as inductors, capacitors, transmission lines, translbrmers and transistors in mm-wave frequency band are discussed. Self-healing technique dealing with PVT variation, res- onant mode switching technique to enhance frequency tuning range of voltage controlled oscillator （VCO） and dual mode technique for power amplifier （PA） efficiency enhancement are introduced. At last, A fully-integrated 60 GHz 5 Gb/s QPSK transceiver with the transmit/receive （T/R） switch in 65nm CMOS process is introduced. The measured error vector magnitude （EVM） of the TX is -21.9 dB while the bit error rate （BER） of the RX with a -52 dBm sine-wave input is below 8e-7 when transmitting/receiving 5 Gb/s data. The transceiver is powered by 1.0 V and 1.2 V supply （except the phase-frequency detector and charge-pump in the frequency synthesizer which are powered by 2.5 V supply） and con- sumes 135 mW in TX mode and 176 mW in RX mode.展开更多
A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system contr...A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.展开更多
文摘A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.
文摘A compact Ka-band monolithic microwave integrated circuit(MMIC) voltage controlled oscillator (VCO) with wide tuning range and high output power,which is based on GaAs PHEMT process,is presented.A method is introduced to reduce the chip size and to increase the bandwidth of operation.The procedure to design a MMIC VCO is also described here.The measured oscillating frequency of the MMIC VCO is 36±1.2GHz and the output power is 10±1dBm.The fabricated MMIC chip size is 1.3mm×1.0mm.
文摘We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital controller, the proposed DPWM can not only offer temperature/process-independent pulse widths, but also operate at a much higher clock frequency than the existing delay-line/counter DPWM structure. Post-simulation results show that with our DPWM, the system clock frequency reaches 156.9MHz while the worst variation,in a temperature range of 0 to 100℃under all process corners,is only± 9.4%.
基金The National Natural Science Foundation of China(No. 60974116 )the Research Fund of Aeronautics Science (No.20090869007)Specialized Research Fund for the Doctoral Program of Higher Education (No. 200902861063)
文摘In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.
文摘A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range （from 1. 8998 to 2. 2335GHz） through a combination of analog and digital tuning techniques （4-bit binary switch-capacitor array）. The measured phase noise is - 118.17dBc/Hz at a 1MHz offset from a 2. 158GHz carrier. With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits. The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors. The VCO draws a current of about 2. lmA from a 1.8V power supply and works normally with a 1.5V power supply.
基金supported in part by the National Natural Science Foundation of China under Grant 61331003 and Grant 61222405
文摘This paper lenges in the design of discusses some chal- millimeter-wave （mln- wave） circuits and systems for 5th generation （5G） wireless systems in CMOS process. The properties of some passive and active devices such as inductors, capacitors, transmission lines, translbrmers and transistors in mm-wave frequency band are discussed. Self-healing technique dealing with PVT variation, res- onant mode switching technique to enhance frequency tuning range of voltage controlled oscillator （VCO） and dual mode technique for power amplifier （PA） efficiency enhancement are introduced. At last, A fully-integrated 60 GHz 5 Gb/s QPSK transceiver with the transmit/receive （T/R） switch in 65nm CMOS process is introduced. The measured error vector magnitude （EVM） of the TX is -21.9 dB while the bit error rate （BER） of the RX with a -52 dBm sine-wave input is below 8e-7 when transmitting/receiving 5 Gb/s data. The transceiver is powered by 1.0 V and 1.2 V supply （except the phase-frequency detector and charge-pump in the frequency synthesizer which are powered by 2.5 V supply） and con- sumes 135 mW in TX mode and 176 mW in RX mode.
基金Project(2011912004)supported by the Major Program of the Economic & Information Commission Program of Guangdong Province,ChinaProjects(2011B010700065,2011A090200106)supported by the Major Program of the Department of Science and Technology of Guangdong Province,China
文摘A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.
