CMOS有源电感并联的前馈共栅跨阻放大电路

设计了一种改进的前馈共栅 (Modified Feedforward Common Gate, MFCG) 跨阻放大电路,通过使用 CMOS 有源电感与前馈共栅 (Feedforward Common Gate, FCG) 跨阻放大电路中的共源放大级并联,使跨阻放大电路的带宽和跨阻增益均得到有效提升。基于 TSMC 60 nm CMOS 工艺在Cadence 软件平台对 MFCG 跨阻放大电路进行仿真分析和版图设计。仿真结果表明在电源电压为 1.8 V,光电二极管结电容为 200 fF 的情况下,放大电路的-3 dB 带宽为 17.2 GHz,跨阻增益为 55 dBΩ,在带宽内等效输入噪声电流谱密度小于 55pA√Hz,电路功耗为 3.7 mW,电路版图面积为 0.002 9 mm^(2)。结果表明:所设计的 MFCG 跨阻放大电路具有跨阻增益高、带宽大、版图面积小等优点,可用于 20 Gb/s光纤通信系统的光接收机电路。

Design of a 12-Gbit/s CMOS DNFFCG differential transimpedance amplifier

A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(VSR)optoelectronic integrated circuit(OEIC)receiver.The dominant pole of the input node is shifted up to a high frequency,and thus the bandwidth of the CMOS DNFFCG TIA is improved.Besides,two negative feedback loops are used to reduce the input impedance and further increase the bandwidth.The proposed TIA was fabricated using TSMC 0.18 jxm CMOS technology.The whole circuit has a compact chip area,the core area of which is only 0.003 6 mm2.The power consumption is 14.6 mW excluding 2-stage differential buffers.The test results indicate that the 3 dB bandwidth of 9 GHz is achieved with a 1 8 V supply voltage and its trans-impedance gain is 49.2 dBH.The measured average equivalent input noise current density is 28.1 pA H z12.Under the same process conditions,the DNFFCG has better gain bandwidth product compared with those in the published papers.

10Gb/s CMOS工艺光接收机前端放大器的设计

本文采用TSMC 0.18μm CMOS工艺,设计了一种应用于SDH系统STM-64(10Gb/s)光接收机的前端放大器。在跨阻放大器中,在共栅前馈结构的基础上加入有源电感,设计了一种宽带的跨阻输入级;跨阻放大器的增益级和限幅放大器核心单元采用三阶交叉有源反馈结构来扩展带宽。