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ISM Band Medium Power Amplifier 被引量:1
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作者 白大夫 刘训春 +1 位作者 袁志鹏 钱永学 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2004年第6期626-632,共7页
With the large-signal model extracted from the InGaP/GaAs HBT with three fingers,a three-stage,class AB power amplifier at ISM band is designed.Through the optimization of the traditional bias network,the gain compres... With the large-signal model extracted from the InGaP/GaAs HBT with three fingers,a three-stage,class AB power amplifier at ISM band is designed.Through the optimization of the traditional bias network,the gain compression at the low input power level is eliminated successfully.At 3.5V of supply voltage of the power amplifier after optimization exhibits 30dBm of maximum linear output power,43.4% of power added efficiency 109.7mA of a quite low quiescent bias current ,29.1dB of the corresponding gain,and -100dBc of the adjacent channel power rejection (ACPR) at the output power of 30dBm. 展开更多
关键词 heterojunction bipolar transistor power amplifier bias network gain compression quiescent bias current
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UHF power amplifier design in 0.35μm SiGe BiCMOS
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作者 宋家友 Li Zhiqun Wang Zhigong 《High Technology Letters》 EI CAS 2009年第2期147-150,共4页
A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe BiCMOS process.It was fully integrated excluding the inductors and the output matching network.Under a single 3.3V... A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe BiCMOS process.It was fully integrated excluding the inductors and the output matching network.Under a single 3.3V supply voltage,the off-chip bonding test results indicated that the circuit has a smallsignal gain of more than 24dB,the input and output reflectance are less than- 24dB and-10dB,re-spectively,and the maximal output power is 23.5 dBm.At output power of 23.1 dBm,the PAE(poweradded efficiency)is 30.2%,the IMD2 and IMD3 are less than- 32 dBc and-46 dBc,respectively.The chip size is 1.27mm ×0.9mm. 展开更多
关键词 power amplifier SIGE BICMOS heterojuncfion bipolar transistor
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基于用电采集系统的配变停电研究分析 被引量:1
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作者 陈春 付明 +3 位作者 赵景涛 尹宏源 杜健 郑涛 《自动化与仪器仪表》 2019年第3期174-177,181,共5页
传统用电采集系统的配变停电智能控制研究中,变停电信息采集准确率低,系统稳定性较差。为了提高用电采集系统的配变停电智能控制性能,进行用电采集系统的智能优化设计,提出基于PCI总线传输控制和集成DSP信息处理的用电采集系统设计方案... 传统用电采集系统的配变停电智能控制研究中,变停电信息采集准确率低,系统稳定性较差。为了提高用电采集系统的配变停电智能控制性能,进行用电采集系统的智能优化设计,提出基于PCI总线传输控制和集成DSP信息处理的用电采集系统设计方案,结合模糊PID进行配变电智能控制。系统结构组成包括传感模块、电能总线传输控制模块、功率增益放大模块、配电调度模块和集成控制模块等,采用电阻测功仪进行配变停电信息采集,对采集的传感信息进行智能配变和集成调度,在ARM Cortex-M3内核中进行用电采集系统的集成开发,结合集成DSP信息处理芯片进行系统的硬件集成设计,采用模糊PID控制模块进行用电采集系统的配变停电智能控制设计。系统测试结果表明,采用该系统进行用电采集的准确性较好,配变停电的智能控制品质较高,为电力系统的发展提供了一定的科学支撑。 展开更多
关键词 用电采集系统 配变停电 控制 嵌入式 DSP 功率增益放大
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