再磨作业球磨机功耗法选型计算探讨

选矿厂设计中磨机选型一直是设计核心,常用的方法有容积法、功耗法、仿真法等。功耗法是目前球磨机选型应用最为广泛的方法,随着功耗法计算的经验积累及选矿厂球磨机规格越来越大,实际生产中发现采用功耗法计算再磨作业的球磨机误差较大,需要根据再磨流程对计算公式中的输入参数和校正系数进行一定调整。同时在设计中也要对循环负荷、分级效率等因素进行充分考虑,使再磨系统设计选型尽可能符合实际生产规律。

防爆电器功耗法的计算及测试方法

本文针对防爆电器功耗法的应用、计算及测试方法做一详细论述。

选择磨机的直接功耗计算法与相对功耗计算法

以一水硬铝石为实例 ,介绍了采用功耗法选择磨机的两种计算方法 ,即直接功耗法和相对功耗法。

功耗法在半自磨机选型中的应用

功耗法已成为磨机选型的主要方法。目前人们比较熟悉的是功耗法在球磨机选型中的应用,即通过邦德功理论计算球磨机的单位功耗来进行选型。而应用功耗法进行半自磨机的选型研究在国内还较少。重点介绍了几种国际上常用的半自磨机单位功耗计算模型,并根据日常选型工作提出了新的半自磨机单位功耗计算模型。最后,通过实例演示了如何应用功耗法进行半自磨机选型。

A New Cochlear Prosthetic System with an Implanted DSP

This paper proposes a cochlear prosthetic system with an implanted digital signal processor （DSP）. This system transmits voice-band signals with a low data rate through the wireless link, free of the data-rate limitation and suitable for future development. By optimizing the speech processing algorithm and the DSP hardware design, the implanted DSP manages to execute the continuous interleaved sampling （CIS） algorithm at a clock frequency of 3MHz and a power consumption of only 1.91mW. With an analytic power-transmission efficiency of the wireless inductive link （40%）, the power overhead caused by the implanted DSP is derived as 2.87roW,which is trivial when compared with the power consumption of existing cochlear prosthetic systems （tens of milliwatts）. With the DSP implanted,this new system can.be easily developed into a fully implanted cochlear prosthesis.

Low Power Polarity Conversion Based on the Whole Annealing Genetic Algorithm

For an n-variable logic function,the power dissipation and area of the REED-MULLER （RM） circuit corresponding to each polarity are different. Based on the propagation algorithm of signal probability,the decomposition algorithm of a multi-input XOR/AND gate,and the multiple segment algorithm of polarity conversion,this paper successfully applies the whole annealing genetic algorithm （WAGA） to find the best polarity of an RM circuit. Through testing eight large-scale circuits from the Microelectronics Center North Carolina （MCNC） Benchmark, the SYNOPSYS synthesis results show that the RM circuits corresponding to the best polarity found using the proposed algorithm attain average power,area,and max delay savings of 77.2% ,62.4% ,and 9.2% respectively,compared with those under polarity 0.

A Novel Divider Based on Dual-Bit Algorithm

A novel divider based on dual-bit algorithm and its VLSI implementation are presented.Compared with the divider of MIPS microprocessor,it decreases the average executing cycles by 52.5% while its maximum delay is almost the same and its transistor count increases by 60%.Furthermore,the simulation result indicates that the power consumption decreases to 11.3% with the same processing ability.

DESIGN OF TERNARY COUNTER BASED ON ADIABATIC DOMINO CIRCUIT

By researching the ternary counter and low power circuit design method, a novel design of low power ternary Domino counter on switch-level is proposed. Firstly, the switch-level structure expression of ternary loop operation circuit with enable pin is derived according to the switch-signal theory, and the one bit ternary counter is obtained combining the ternary adiabatic Domino literal operation circuit and buffer. Then the switch-level structure expression of enable signal circuit is derived, and the four bits ternary counter is obtained by cascade connection. Finally, the circuit is simulated by Spice tool and the output waveforms transform in proper order indicating that the logic function is correct. The energy consumption of the four bits ternary adiabatic Domino counter is 63% less than the conventional Domino counterpart.

Partition-based Low Power DFT Methodology for System-on-chips

This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to low power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation （EDA） tools from Synopsy~ to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-ou-chips （SOC）. The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test m ADVANTEST.

Low energy consumption depth control method of self-sustaining intelligent buoy

Aiming at the contradiction between the depth control accuracy and the energy consumption of the self-sustaining intelligent buoy,a low energy consumption depth control method based on historical array for real-time geostrophic oceanography(Argo)data is proposed.As known from the buoy kinematic model,the volume of the external oil sac only depends on the density and temperature of seawater at hovering depth.Hence,we use historical Argo data to extract the fitting curves of density and temperature,and obtain the relationship between the hovering depth and the volume of the external oil sac.Genetic algorithm is used to carry out the optimal energy consumption motion planning for the depth control process,and the specific motion strategy of depth control process is obtained.Compared with dual closed-loop fuzzy PID control method and radial basis function(RBF)-PID method,the proposed method reduces energy consumption to 1/50 with the same accuracy.Finally,a hardware-in-the-loop simulation system was used to verify this method.When the error caused by fitting curves is not considered,the average error is 2.62 m,the energy consumption is 3.214×10^(4)J,and the error of energy consumption is only 0.65%.It shows the effectiveness and reliability of the method as well as the advantages of comprehensively considering the accuracy and energy consumption.

Low-power Analog VLSI Implementation of Wavelet Transform

For applications requiring low-power,low-voltage and real-time,a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed. Marr wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained. The circuits of implementating Marr wavelet transform are composed of analog filter whose impulse response is the required wavelet. The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks. SPICE simulations indicate an excellent approximations of ideal wavelet.

A Game Theoretic Approach for Inter-Network Interference Mitigation in Wireless Body Area Networks

Wireless Body Area Network(WBAN) is an emerging technology to provide real-time health monitoring and ubiquitous healthcare services. In many applications, multiple wireless body area networks have to coexist in a small area, resulting in serious inter-network interference. This not only reduces network reliability that is especially important in emergency medical applications, but also consumes more power of WBANs. In this paper, an inter-network interference mitigation approach based on a power control algorithm is proposed. Power control is modeled as a non-cooperative game, in which both inter-network interference and energy efficiency of WBANs are considered. The existence and uniqueness of Nash Equilibrium in the game are proved, and an optimal scheme based on best response is proposed to find its Nash Equilibrium. By coordinating the transmission power levels among networks under interference environment, the total system throughput can be increased with minimum power consumed. The effectiveness of the proposed method has been illustrated by simulation results, where the performance of the proposed approach is evaluated in terms of overall utility and power efficiency and convergence speed.

某大型铜矿磨矿试验及选型技术应用研究

磨矿试验和磨机选型技术是确定磨矿设备规格和工艺参数的基础。基于碎磨试验参数,采用功耗法进行了磨机选型计算,确定了满足项目工艺要求的磨机规格和电动机安装功率,然后结合项目投产后不同生产阶段的磨矿运行参数,分析了不同工艺流程的应用情况,并结合生产实践进行不同碎磨工艺的优化探讨和分析。同时,针对半自磨机顽石开路流程,提出了半自磨机顽石产率的合理取值是项目设计的关键。

磨矿试验及选型技术在某铅锌矿的应用研究

磨矿试验及磨机选型是确定磨矿工艺参数的关键。针对某铅锌矿的矿石性质,通过磨矿试验,采用功耗法进行了磨机选型计算,确定了合理的磨机规格和电动机安装功率,并对处理量进行了预测计算。结合该矿山投产后的运行数据,验证了基于磨矿试验的磨机选型计算参数与磨矿运行参数基本一致。同时,基于选型计算参数与矿山投产初期运行参数的对比分析,提出了磨矿工艺优化措施,并已成功应用于该矿山优化提产实践中。