Using Technology Computer-Aided Design(TCAD) 3-D simulation,the single event effect(SEE) of 25 nm raised source-drain FinFET is studied.Based on the calibrated 3-D models by process simulation,it is found that the amo...Using Technology Computer-Aided Design(TCAD) 3-D simulation,the single event effect(SEE) of 25 nm raised source-drain FinFET is studied.Based on the calibrated 3-D models by process simulation,it is found that the amount of charge collected increases linearly as the linear energy transfer(LET) increases for both n-type and p-type FinFET hits,but the single event transient(SET) pulse width is not linear with the incidence LET and the increasing rate will gradually reduce as the LET increases.The impacts of wafer thickness on the charge collection are also analyzed,and it is shown that a larger thickness can bring about stronger charge collection.Thus reducing the wafer thickness could mitigate the SET effect for FinFET technology.展开更多
A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the...A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors.For the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional one.The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.展开更多
Single-event transient pulse quenching （Quenching effect） is employed to effectively mitigate WSET （SET pulse width）. It en- hanced along with the increased charge sharing which is norm for future advanced technol...Single-event transient pulse quenching （Quenching effect） is employed to effectively mitigate WSET （SET pulse width）. It en- hanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, param- eter variation is another serious issue that significantly affects circuit＇s performance and single-event response. Monte Carlo simulations combined with TCAD （Technology Computer-Aided Design） simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. Studies show that charge sharing induce a wider WSET spread range. The difference of WSET range between no quenching and quenching is smaller in NMOS （N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor） simulation than that in PMOS＇ （P-Channel Met- N-Oxide-Semiconductor Field-Effect Transistor）, so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. The individual parameter analysis indicates that gate oxide thickness （TOXE） and channel length variation （XL） mostly affect SET response of combinational circuits. They bring 14.58% and 19.73% average WSET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases.展开更多
基金supported by the National Natural Science Foundation of China (Grant Nos. 60836004,61006070,and 61076025)
文摘Using Technology Computer-Aided Design(TCAD) 3-D simulation,the single event effect(SEE) of 25 nm raised source-drain FinFET is studied.Based on the calibrated 3-D models by process simulation,it is found that the amount of charge collected increases linearly as the linear energy transfer(LET) increases for both n-type and p-type FinFET hits,but the single event transient(SET) pulse width is not linear with the incidence LET and the increasing rate will gradually reduce as the LET increases.The impacts of wafer thickness on the charge collection are also analyzed,and it is shown that a larger thickness can bring about stronger charge collection.Thus reducing the wafer thickness could mitigate the SET effect for FinFET technology.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60836004 and 60906014)Hunan Provincial Innovation Foundation For Postgraduate (Grant No. CX2011B026)
文摘A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors.For the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional one.The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.
基金supported by the Harbin Science and Innovation Research.(Grant No.2012RFXXG042)
文摘Single-event transient pulse quenching （Quenching effect） is employed to effectively mitigate WSET （SET pulse width）. It en- hanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, param- eter variation is another serious issue that significantly affects circuit＇s performance and single-event response. Monte Carlo simulations combined with TCAD （Technology Computer-Aided Design） simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. Studies show that charge sharing induce a wider WSET spread range. The difference of WSET range between no quenching and quenching is smaller in NMOS （N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor） simulation than that in PMOS＇ （P-Channel Met- N-Oxide-Semiconductor Field-Effect Transistor）, so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. The individual parameter analysis indicates that gate oxide thickness （TOXE） and channel length variation （XL） mostly affect SET response of combinational circuits. They bring 14.58% and 19.73% average WSET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases.
