双框架变速率控制力矩陀螺(Double-gimbaled variable-speed control moment gyroscope,DGVSCMG)是航天器重要姿态执行机构。它由内外框架速率伺服系统和转速可变的高速转子组成,有飞轮和控制力矩陀螺(Control moment gyroscope,CMG)两...双框架变速率控制力矩陀螺(Double-gimbaled variable-speed control moment gyroscope,DGVSCMG)是航天器重要姿态执行机构。它由内外框架速率伺服系统和转速可变的高速转子组成,有飞轮和控制力矩陀螺(Control moment gyroscope,CMG)两种工作模式。在两种工作模式下,框架伺服系统都会受到不匹配干扰,降低速率伺服性能,影响DGVSCMG的输出力矩精度,需要加以抑制。为了提高框架系统抗扰性能,并保证系统角速率伺服精度,提出一种基于干扰观测器(Disturbance observer,DO)与状态反馈的解耦控制方法。在对DGVSCMG框架系统的不匹配扰动建模与分析的基础上,利用鲁棒控制思想设计控制器与干扰观测器参数,并对全局系统进行了稳定性分析。仿真和试验结果表明,所提出的方法可有效抑制双框架伺服系统干扰,并满足DGVSCMG框架系统的性能要求。展开更多
Noise and mismatch are important error sources in pipeline ADCs,so careful calculation and system simulation are carried out using Matlab software. To reduce power consumption while not lose performance, the amplifier...Noise and mismatch are important error sources in pipeline ADCs,so careful calculation and system simulation are carried out using Matlab software. To reduce power consumption while not lose performance, the amplifiers with the same structure are biased with one bias circuit, and a cascode compensation is adopted. A 10bit 50MS/s pipeline ADC, which can be used in CMOS image sensor systems with large pixel array,is designed and tested by using 0.35tzm 4M-2P CMOS process. According to test results, power consumption is only 42mW and SINAD is 45.69dB when sampling frequency is 50MHz. A balance between performance and power consumption is achieved.展开更多
文摘双框架变速率控制力矩陀螺(Double-gimbaled variable-speed control moment gyroscope,DGVSCMG)是航天器重要姿态执行机构。它由内外框架速率伺服系统和转速可变的高速转子组成,有飞轮和控制力矩陀螺(Control moment gyroscope,CMG)两种工作模式。在两种工作模式下,框架伺服系统都会受到不匹配干扰,降低速率伺服性能,影响DGVSCMG的输出力矩精度,需要加以抑制。为了提高框架系统抗扰性能,并保证系统角速率伺服精度,提出一种基于干扰观测器(Disturbance observer,DO)与状态反馈的解耦控制方法。在对DGVSCMG框架系统的不匹配扰动建模与分析的基础上,利用鲁棒控制思想设计控制器与干扰观测器参数,并对全局系统进行了稳定性分析。仿真和试验结果表明,所提出的方法可有效抑制双框架伺服系统干扰,并满足DGVSCMG框架系统的性能要求。
文摘Noise and mismatch are important error sources in pipeline ADCs,so careful calculation and system simulation are carried out using Matlab software. To reduce power consumption while not lose performance, the amplifiers with the same structure are biased with one bias circuit, and a cascode compensation is adopted. A 10bit 50MS/s pipeline ADC, which can be used in CMOS image sensor systems with large pixel array,is designed and tested by using 0.35tzm 4M-2P CMOS process. According to test results, power consumption is only 42mW and SINAD is 45.69dB when sampling frequency is 50MHz. A balance between performance and power consumption is achieved.