Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) using P+ (phosphor ion) implantation technology is successfully fabricated. P+ implantation into SiGe virtual substrate induces a narrow de...Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) using P+ (phosphor ion) implantation technology is successfully fabricated. P+ implantation into SiGe virtual substrate induces a narrow defect region slightly below the SiGe/Si interface,which gives rise to strongly enhanced strain relaxation of SiGe virtual substrate. X-Ray Diffraction (XRD) tests show that the degree of relaxation of SiGe layer is 96% while 85% before implantation. After annealed,the sample appeared free of Threading Dislocation densities (TDs) within the SiGe layer to the limit of Trans-mission Electron Microscopy (TEM) analysis. Atomic Force Microscope (AFM) test of strained Si channel surface shows that Root Mean Square (RMS) is 1.1nm. The Direct Current (DC) characters measured by HP 4155B indicate that the maximum saturated transconductance is twice bigger than that of bulk Si PMOSFET.展开更多
This research analyzes the growth impacts promoted by C class in the process of the freezing of the Brazilian industry and increased imports. This emerging market, called class C, which is incorporated in part by the ...This research analyzes the growth impacts promoted by C class in the process of the freezing of the Brazilian industry and increased imports. This emerging market, called class C, which is incorporated in part by the low-income segment, presents distinct characteristics and needs and for this precise reason eventually burdens the short-term production of Brazilian companies, which feel the need to opt for the importation of basic commodities, manufactured, and semi-manufactured goods, in order to maintain a market share and return on their investments. Although this fact is actually part of a trend of global economic transformation, here it is due to a number of irregular actions taken by the Brazilian government facing a short-term political need. Stemming from quantitative researches and qualitative data, this paper sought to learn more about the consumers' profile and draw up some recommendations for the organizations, in order to be better prepared to face this new demand. This paper also sought to know the actions already undertaken by a large cosmetics company, parts of whose products aim at class C.展开更多
Here we report a simple and scalable method to fabricate high performance thin-film field-effect transistors(FETs) with high yield based on chemically functionalized single-walled carbon nanotubes(SWNTs) by organic ra...Here we report a simple and scalable method to fabricate high performance thin-film field-effect transistors(FETs) with high yield based on chemically functionalized single-walled carbon nanotubes(SWNTs) by organic radical initiators.The UV-Vis-NIR spectra,Raman spectra and electrical characterization demonstrated that metallic species in CoMoCat 65 and HiPco SWNTs could be effectively eliminated after reaction with some organic radical initiators.The effects of the substrate properties on the electrical properties of FET devices were investigated,and the results showed that the electrical properties of FET devices fabricated on high hydrophobic substrates were better than those on low hydrophobic substrates.Furthermore,it was found that FET devices based on 1,1'-azobis(cyanocyclohexane)(ACN)-modified CoMoCat 65 SWNTs exhibited more excellent electrical performance with effective mobility of ~11.8 cm2/Vs and on/off ratio of ~2×105 as compared with benzoyl peroxide(BPO)-modified CoMoCat 65 SWNTs and lauoryl peroxideand(LPO)-modified HiPco SWNTs,likely due to the introduction of the electron-withdrawing groups(CN group) on the SWNT surface.This method does not require nontrivial reaction conditions or complicated purification after reaction,therefore promising low-cost production of high-performance devices for macroelectronics.展开更多
Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field ...Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.展开更多
基金Supported by the Funds of National Key Laboratory of Analog IC (2000JS09.3.1.DZ02).
文摘Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) using P+ (phosphor ion) implantation technology is successfully fabricated. P+ implantation into SiGe virtual substrate induces a narrow defect region slightly below the SiGe/Si interface,which gives rise to strongly enhanced strain relaxation of SiGe virtual substrate. X-Ray Diffraction (XRD) tests show that the degree of relaxation of SiGe layer is 96% while 85% before implantation. After annealed,the sample appeared free of Threading Dislocation densities (TDs) within the SiGe layer to the limit of Trans-mission Electron Microscopy (TEM) analysis. Atomic Force Microscope (AFM) test of strained Si channel surface shows that Root Mean Square (RMS) is 1.1nm. The Direct Current (DC) characters measured by HP 4155B indicate that the maximum saturated transconductance is twice bigger than that of bulk Si PMOSFET.
文摘This research analyzes the growth impacts promoted by C class in the process of the freezing of the Brazilian industry and increased imports. This emerging market, called class C, which is incorporated in part by the low-income segment, presents distinct characteristics and needs and for this precise reason eventually burdens the short-term production of Brazilian companies, which feel the need to opt for the importation of basic commodities, manufactured, and semi-manufactured goods, in order to maintain a market share and return on their investments. Although this fact is actually part of a trend of global economic transformation, here it is due to a number of irregular actions taken by the Brazilian government facing a short-term political need. Stemming from quantitative researches and qualitative data, this paper sought to learn more about the consumers' profile and draw up some recommendations for the organizations, in order to be better prepared to face this new demand. This paper also sought to know the actions already undertaken by a large cosmetics company, parts of whose products aim at class C.
基金supported by the Scientific Research Fund of Hunan Provincial Education Department(09B084)the Opening Project of Key Laboratory of Photochemical Conversion and Optoelectronic Materials,TIPC, Chinese Academy of Sciences(PCOM201114)
文摘Here we report a simple and scalable method to fabricate high performance thin-film field-effect transistors(FETs) with high yield based on chemically functionalized single-walled carbon nanotubes(SWNTs) by organic radical initiators.The UV-Vis-NIR spectra,Raman spectra and electrical characterization demonstrated that metallic species in CoMoCat 65 and HiPco SWNTs could be effectively eliminated after reaction with some organic radical initiators.The effects of the substrate properties on the electrical properties of FET devices were investigated,and the results showed that the electrical properties of FET devices fabricated on high hydrophobic substrates were better than those on low hydrophobic substrates.Furthermore,it was found that FET devices based on 1,1'-azobis(cyanocyclohexane)(ACN)-modified CoMoCat 65 SWNTs exhibited more excellent electrical performance with effective mobility of ~11.8 cm2/Vs and on/off ratio of ~2×105 as compared with benzoyl peroxide(BPO)-modified CoMoCat 65 SWNTs and lauoryl peroxideand(LPO)-modified HiPco SWNTs,likely due to the introduction of the electron-withdrawing groups(CN group) on the SWNT surface.This method does not require nontrivial reaction conditions or complicated purification after reaction,therefore promising low-cost production of high-performance devices for macroelectronics.
文摘Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.