This paper optimizes the buried channel charge-coupled device(BCCD) structure fabricated by complementary metal oxide semiconductor(CMOS) technology. The optimized BCCD has advantages of low noise, high integration an...This paper optimizes the buried channel charge-coupled device(BCCD) structure fabricated by complementary metal oxide semiconductor(CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency(CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V.展开更多
Direct integration of high-mobility III-V compound semiconductors with existing Si-based complementary metal-oxide-semiconductor （CMOS） processing platforms presents the main challenge to increasing the CMOS perform...Direct integration of high-mobility III-V compound semiconductors with existing Si-based complementary metal-oxide-semiconductor （CMOS） processing platforms presents the main challenge to increasing the CMOS performance and the scaling trend. Silicon hetero-nanowires with integrated III-V segments are one of the most promising candidates for advanced nano-optoelectronics, as first demonstrated using molecular beam epitaxy techniques. Here we demonstrate a novel route for InAs/Si hybrid nanowire fabrication via millisecond range liquid-phase epitaxy regrowth using sequential ion beam implantation and flash-lamp annealing. We show that such highly mismatched systems can be monolithically integrated within a single nanowire. Optical and microstructural investigations confirm the high quality hetero-nanowire fabrication coupled with the formation of atomically sharp interfaces between Si and InAs segments. Such hybrid systems open new routes for future high-speed and multifunctional nanoelectronic devices on a single chip.展开更多
基金supported by the National Natural Science Foundation of China(Nos.61306070,61404090 and 61674115)
文摘This paper optimizes the buried channel charge-coupled device(BCCD) structure fabricated by complementary metal oxide semiconductor(CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency(CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V.
文摘Direct integration of high-mobility III-V compound semiconductors with existing Si-based complementary metal-oxide-semiconductor （CMOS） processing platforms presents the main challenge to increasing the CMOS performance and the scaling trend. Silicon hetero-nanowires with integrated III-V segments are one of the most promising candidates for advanced nano-optoelectronics, as first demonstrated using molecular beam epitaxy techniques. Here we demonstrate a novel route for InAs/Si hybrid nanowire fabrication via millisecond range liquid-phase epitaxy regrowth using sequential ion beam implantation and flash-lamp annealing. We show that such highly mismatched systems can be monolithically integrated within a single nanowire. Optical and microstructural investigations confirm the high quality hetero-nanowire fabrication coupled with the formation of atomically sharp interfaces between Si and InAs segments. Such hybrid systems open new routes for future high-speed and multifunctional nanoelectronic devices on a single chip.
