This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit,...This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.展开更多
A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller th...A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage.With this 2D array of differential paired eFuse OTP memory cells,we design a 32-bit eFuse OTP memory IP.We use a sense amplifier based D F/F circuit as the BL(bit-line)SA(sense amplifier)and design a sensing margin test circuit with a variable pull-up load.It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.展开更多
基金Supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2012ZX03004008)
文摘This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.
基金Project supported by the Second Stage of Brain Korea 21 Projectssupported by Industrial Strategic Technology Development Program funded by the Ministry of Knowledge Economy (MKE,Korea)(10039239,"Development of Power Management System SoC Supporting Multi-Battery-Cells and Multi-Energy-Sources for Smart Phones and Smart Devices")
文摘A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage.With this 2D array of differential paired eFuse OTP memory cells,we design a 32-bit eFuse OTP memory IP.We use a sense amplifier based D F/F circuit as the BL(bit-line)SA(sense amplifier)and design a sensing margin test circuit with a variable pull-up load.It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.
