To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel ske...To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.展开更多
This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three ...This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three coprocessors that are used for synchronization, FFT and channel decoder. In this MIMO OFDM system, the Zero Correlation Zone （ZCZ） code is used as the synchronization word preamble of packet in the physical layer in order to avoid the interference from other transmitting antennas. Furthermore, a simple channel estimation algorithm is proposed which is appropriate tbr the SIMD DSP computation.展开更多
基金Project (No. 2005AA1Z1271) supported by the Hi-Tech Research and Development Program (863) of China
文摘To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.
基金Supported by the National Natural Science Foundation of China (No.60476013).
文摘This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three coprocessors that are used for synchronization, FFT and channel decoder. In this MIMO OFDM system, the Zero Correlation Zone （ZCZ） code is used as the synchronization word preamble of packet in the physical layer in order to avoid the interference from other transmitting antennas. Furthermore, a simple channel estimation algorithm is proposed which is appropriate tbr the SIMD DSP computation.
