石英压电微天平测定加碘盐中的碘

石英压电微天平测定加碘盐中的碘陈波１张莹２潘振球１冯家力１姚守拙３近３０年来，石英压电微天平由于具有高的灵敏度和测量精度而得到极快发展。ＡＴ切型的石英压电晶体作为化学微天平质量检测可达纳克数量级，其在生物材料测定、电化学研究、食品分析等领域中的应用愈...

Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector

A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.

A Low Jitter PLL in a 90nm CMOS Digital Process

A low jitter phase-locked loop （PLL） that does not need analog resistors and capacitors is designed and fabrica- ted in a 90nm CMOS digital process. The metal parasitic capacitor is used in the PLL loop filter. Test results show that when the PLL is locked on 1. 989GHz, the RMS jitter is 3. 7977ps, the peak-to-peak jitter is 31. 225ps, and the power con- sumption is about 9mW. The locked output frequency range is from 125MHz to 2.7GHz.

Low phase noise LC VCO design in CMOS technology

This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.

An Accurate 1.08GHz CMOS LC Voltage-Controlled Oscillator

An accurate 1.08GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process.A new convenient method of calculating oscillator period is presented.With this period calculation technique,the frequency tuning curves agree well with the experiment.At a 3.3V supply,the LC-VCO measures a phase noise of -82.2dBc/Hz at a 10kHz frequency offset while dissipating 3.1mA current.The chip size is 0.86mm×0.82mm.

Gate Annealing of an Enhancement-Mode InGaP/AlGaAs/InGaAs PHEMT

For enhancement-mode InGaP/A1GaAs/InGaAs PHEMTs,gate annealing is conducted between gate structures of Ti/Pt/Au and Pt/Ti/Pt/Au. Comparison is made after thermal annealing and an optimum annealing process is ob- tained. Using the structure of Ti/Pt/Au, about a 200mV positive shift of threshold voltage is achieved by thermal annea- ling at 320℃ for 40min in N2 ambient. Finally, a stable and consistent enhancement-mode PHEMT is produced successfully with higher threshold voltage.

Design of a 2.5GHz Low Phase-Noise LC-VCO in 0.35μm SiGe BiCMOS

This paper introduces a 2.5GHz low phase-noise cross-coupled LC-VCO realized in 0.35μm SiGe BiCMOS technology. The conventional definition of a VCO operating regime is revised from a new perspective. Analysis shows the importance of inductance and bias current selection for oscillator phase noise optimization. Differences between CMOS and BJT VCO design strategy are then analyzed and the conclusions are summarized. In this implementation, bonding wires form the resonator to improve the phase noise performance. The VCO is then integrated with other components to form a PLL frequency synthesizer with a loop bandwidth of 30kHz. Measurement shows a phase noise of - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from a 2.5GHz carrier. At a supply voltage of 3V, the VCO core consumes 8mA. To our knowledge,this is the first differential cross-coupled VCO in SiGe BiCMOS technology in China.

A 2.4GHz CMOS Quadrature Voltage-Controlled Oscillator Based on Symmetrical Spiral Inductors and Differential Diodes

A voltage controlled oscillator (VCO) which can generate 2 4GHz quadrature local oscillating (LO) signals is reported.It combines a LC VCO,realized by on chip symmetrical spiral inductors and differential diodes,and a two stage ring VCO.The principle of this VCO is demonstrated and further the phase noise is discussed in detail.The fabrication of prototype is demonstrated using 0 25μm single poly five metal N well salicide CMOS digital process.The reports show that the novel VCO is can generate quadrature LO signals with a tuning range of more than 300MHz as well as the phase noise--104 33dBc/Hz at 600KHz offset at 2 41GHz (when measuring only one port of differential outputs).In addition,this VCO can work in low power supply voltage and dissipate low power,thus it can be used in many integrated transceivers.

A Compact Ka-Band PHEMT MMIC Voltage Controlled Oscillator

A compact Ka-band monolithic microwave integrated circuit(MMIC) voltage controlled oscillator (VCO) with wide tuning range and high output power,which is based on GaAs PHEMT process,is presented.A method is introduced to reduce the chip size and to increase the bandwidth of operation.The procedure to design a MMIC VCO is also described here.The measured oscillating frequency of the MMIC VCO is 36±1.2GHz and the output power is 10±1dBm.The fabricated MMIC chip size is 1.3mm×1.0mm.

A Monolithic InGaP/GaAs HBT VCO for 5GHz Wireless Applications

A monolithic voltage controlled oscillator （VCO） based on negative resistance principle is presented uti-lizing commercially available InGaP/GaAs hetero-junction bipolar transistor （HBT） technology. This VCO is de-signed for 5GHz-band wireless applications. Except for bypass and decoupled capacitors,no external component is needed for real application. Its measured output frequency range is from 4.17 to 4.56GHz,which is very close to the simulation one. And the phase noise at an offset frequency of 1MHz is -112dBc/Hz. The VCO core dissipates 15.5mW from a 3.3V supply,and the output power ranges from 0 to 2dBm. To compare with other oscillators,the figure of merit is calculated,which is about -173.2dBc/Hz. Meanwhile, the principle and design method of nega-tive resistance oscillator are also discussed.

A wideband low-phase-noise LC VCO for DRM/DAB frequency synthesizer

The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.

A 1.1GHz LC VCO with Automatic Amplitude Control for Tuner Applications

This paper presents an LC VCO with auto-amplitude control （AAC）, in which pMOS FETs are used,and the varactors are directly connected to ground to widen the linear range of Kvco. The AAC circuitry adds little noise to the VCO but provides it with robust performance over a wide temperature and carrier frequency range.The VCO is fabricated in a chartered 50GHz 0.35μm SiGe BiCMOS process. The measurements show that it has - 127. 27dBc/Hz phase noise at 1MHz offset and a linear gain of 32.4MHz/V between 990MHz and 1.14GHz.The whole circuit draws 6. 6mA current from 5V supply.

Adaptive rotor current control for wind-turbine driven DFIG using resonant controllers in a rotor rotating reference frame

This paper proposes an adaptive rotor current controller for doubly-fed induction generator (DFIG), which consists of a proportional (P) controller and two harmonic resonant (R) controllers implemented in the rotor rotating reference frame. The two resonant controllers are tuned at slip frequencies ωslip+ and ωslip-, respectively. As a result, the positive- and negative-sequence components of the rotor current are fully regulated by the PR controller without involving the positive- and negative-sequence decomposition, which in effect improves the fault ride-through (FRT) capability of the DFIG-based wind power generation system during the period of large transient grid voltage unbalance. Correctness of the theoretical analysis and feasibility of the proposed unbalanced control scheme are validated by simulation on a 1.5-MW DFIG wind power generation system.

Research on CMOS Mm-Wave Circuits and Systems for Wireless Communications

This paper lenges in the design of discusses some chal- millimeter-wave （mln- wave） circuits and systems for 5th generation （5G） wireless systems in CMOS process. The properties of some passive and active devices such as inductors, capacitors, transmission lines, translbrmers and transistors in mm-wave frequency band are discussed. Self-healing technique dealing with PVT variation, res- onant mode switching technique to enhance frequency tuning range of voltage controlled oscillator （VCO） and dual mode technique for power amplifier （PA） efficiency enhancement are introduced. At last, A fully-integrated 60 GHz 5 Gb/s QPSK transceiver with the transmit/receive （T/R） switch in 65nm CMOS process is introduced. The measured error vector magnitude （EVM） of the TX is -21.9 dB while the bit error rate （BER） of the RX with a -52 dBm sine-wave input is below 8e-7 when transmitting/receiving 5 Gb/s data. The transceiver is powered by 1.0 V and 1.2 V supply （except the phase-frequency detector and charge-pump in the frequency synthesizer which are powered by 2.5 V supply） and con- sumes 135 mW in TX mode and 176 mW in RX mode.

2.7-4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip

A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.

Noise-Induced Transition in a Voltage-Controlled Oscillator Neuron Model

In the presence of Gaussian white noise,we study the properties of voltage-controlled oscillator neuronmodel and discuss the effects of the additive and multiplicative noise.It is found that the additive noise can accelerate andcounterwork the firing of neuron,which depends on the value of central frequency of neuron itself,while multiplicativenoise can induce the continuous change or mutation of membrane potential.

Design of 622 Mb/s Clock-recovery Monolithic IC for Optical Communication System

A monolithic clock-recovery circuit used in 622 Mb/s optical communication system is designed,which is based on the phase-locked loop theory,and uses bipolar transistor model.It overcomes the shortcoming of clock recovery method based on filter,and implements monolithic clock-recovery IC.The designed circuits include phase detector,voltage-controlled oscillator and loop filter.Among them,the voltage-control oscillator is a modified two-stage ring oscillator,which provides quadrature clock signals and presents wide voltage-controlled range and high voltage-controlling sensitivity.

A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application

A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.

Solution of the Dirac equation with the ring-shaped oscillator potential

The ring-shaped oscillator potential, obtained by replacing the Coulomb part of the Hartmann potential by a harmonic oscillator term, was investigated. Under the equal vector potential and scalar potential, the Dirac equation was solved in spherical coordinate. The exact energy spectrum of the bound states was presented as a solution to the confluent hypergeometric equation by boundary conditions. Furthermore, the normalized angular and radial wave functions were presented.

Development of OPTO-LDR coupled timer based voltage to frequency converter

This paper describes the development of a timer based voltage to frequency converter(V FC).Timer LM555is used in astable multivibrator mode with two OPTO-LDRs(light dependent resistors)in the circuitry.The frequency of timer output waveform which is measured using a digital storage oscillator(DSO)is almost linearly proportional to the applied input voltage.Hence we obtain a linear relationship between the frequency of timer output waveform and the input voltage.Because of its quasi-digital output,the main advantages of this developed converter are linear input-output relationship,small size,easy portabilityand high cost performance.In addition,the timer output waveform can be directly interfaced with personal computer or microprocessor/microcontroller for further processing of the input voltage signal without intervening any analog-to-digital converter(ADC).